| ??? 09/22/05 12:50 Read: times Msg Score: +1 +1 Informative |
#101378 - It's amateurish to reduce noise margins Responding to: ???'s previous message |
Jan said:
Yes. That's why Professionals use a two-transistor double-inverter. That's why professionals choose a solution showing sufficient noise margin! And why not using transistor inverters, when you can use digital transistors for this purpose, like BCR148 for instance, which contains the transistor and two resistors in a single SOT-23 SMD-package? Also, the suggestions I made was not how one should design a circuit, but how the original poster can be helped to find a solution for HIS problem. And where using a double stage transistor inverter could be an overkill in a different circuit, it can help the original poster to solve HIS problem. In fact, if you take a normal Schottky, at 50uA (which is the input low current of 2051) the voltage drop will be barely more than 0.2V (I don't have a collection of datasheets on these, just a quick glance to some BAT5x having guaranteed max. 240mV at 100uA) which gives you a - hopefully comfortable - 0.3V noise margin anyway here... We don't talk about the situation, that the potential at P1.3 has finally reached low level, but whether this can be expected to happen at all. LM339 shows an output low voltage of up to 400mV at 4mA sink current and at 25°C. For full temperature range maximum output low voltage is 700mV. And if Supriya does sink more current into the LM339 than 4mA, which is very probable as I demonstrated in my last post, then this output low voltage can be much higher than 400mV! The critical issue during the transition form high to low level is the transition current. And with up to 750µA transition current voltage drop across a small signal Schottky diode can be up to 400mV (1N6263). So, it's questionable, whether the input voltage will fall under 0.9V at all, which is the maximum input low voltage for the AT89C2051. But who knows, maybe this is not enough, as ground bounces might be really significant in this state-of-the-art circuit, capable of switching at around 1MHz rate... As we often stated here, ground bounce is not a matter of clock frequency but of rise and fall times of signals. And I can assure you, that modern micros like AT89C2051 can produce a lot of ground bounce! Kai, tell me, how much do you think is the worst case LSTTL noise margin... For 74LS-logic low-voltage noise margin is 0.4V. That's enough, for 74LS-logic, because rise and fall times are rather long, so that ground bounce is relatively low. For 74HCMOS on the other hand low-level noise margin is 0.9V. This is higher than for 74LS-logic, because 74HCMOS chips suffer from higher ground bounce, due to shorter rise and fall times and especially due to the 'shot through' phenomenon. And also note, that even the coolest professionals DO use diode-resistor logic even if they are not aware of doing so (look at the TTL-LS gates' input stages). Of course, there's a diode resistor ladder inside 74LS-chips. But what you suggest is the adding of a SECOND diode's voltage drop in series, which will heavily decrease low-voltage noise margin. Sorry for being a little bit emotional but as I said I don't think THIS is a matter which needs more attention and hair-picking. Ground bounce and noise margins is always a matter that needs attention! Not only for rocket science, but just for simple circuits, which neglect the use of a solid ground plane. Fetch a really fast scope and check the ground noise of a microntroller's board not using a solid ground plane. You will be totally shocked!! Kai |
