---Hardware switch debouncer with tristateable outputs a la Dallas semiconductor
---uses shift registers on the switch inputs to detect when they have been
---in a steady state for 4 clock cycles.NINT goes low for two clock cycles
---when all switch inputs (swin) have been debounced and the new switch 
---outputs(swout) are ready.
---each switch input requires 7 registers plus sundry logic for the whole design
---clk should be run at around 100 Hz.Set the value of size to the number of inputs required.
-- Copyright (c) 2006 Jez smith (jez-smith@hotmail.co.uk)
-- All rights reserved
-- All offers of vast amounts of cash to produce your designs should be sent to
-- the above
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-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
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-- Redistributions of source code must retain the above copyright notice,
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-- Neither the name of the author nor the names of other contributors may
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library ieee;

use ieee.std_logic_1164.all;


ENTITY filter IS
        PORT(switch_in : in  std_logic;
             clk       : in  std_logic;
             rst_n     : in  std_logic;
             ready     : out std_logic;
             switch_out: out std_logic);
END filter;
--input filter for each switch
ARCHITECTURE rtl OF filter IS
        signal sr1      : std_logic_vector(4 downto 0);

BEGIN


        process(switch_in,rst_n,clk,sr1)
        begin
                if (rst_n='0') then
                        sr1<="00001";
                elsif rising_edge(clk) then
                        sr1<=sr1(2 downto 0) & switch_in;
                        case sr1 is
                        when "00000"=> switch_out <='0';
                                      ready<='1';
                        when "11111"=> switch_out <='1';
                                      ready<='1';
                        when others=> ready <='0';
                        end case;
                end if;
        end process;
END rtl;

library ieee;

use ieee.std_logic_1164.all;
entity debouncer is
--generates the required number of input filters and simple state machine to generate the interupt.
generic(size:positive :=8);             -- number of debounced inputs/outputs required
port (clk   :in  std_logic;
      rst_n :in  std_logic; --negative reset
      oe_n  :in  std_logic; --negative output enable    
      swin  :in  std_logic_vector(size-1 downto 0);  --switch inputs
      swout :out std_logic_vector(size-1 downto 0);  --tristated switch outputs
      nint  :out std_logic); -- negative going interrupt
end debouncer;
architecture rtl of debouncer is


component filter is
        port(switch_in : in  std_logic;
             clk       : in  std_logic;
             rst_n     : in  std_logic;
             ready     : out std_logic;
             switch_out: out std_logic);
end component;

signal max_arry, new_sw_state,sw_state,old_sw_state,sw_ready : std_logic_vector(size-1 downto 0);
signal switch_ready :std_logic;
begin

swout<= new_sw_state when (oe_n='0') else (others=>'Z');
switch_ready<= '1' when (max_arry = sw_ready) else '0';

gen_int: process(new_sw_state,sw_state,old_sw_state,switch_ready,clk)
begin

        if falling_edge(clk) and switch_ready='1' then
                old_sw_state<=sw_state;
                sw_state<=new_sw_state;
                if old_sw_state/=new_sw_state then
                        nint<='0';
                else
                        nint<='1';
                end if;
        end if;
end process;

filters: for i in (size-1) downto 0 generate
        filt : filter port map (swin(i),clk,rst_n,sw_ready(i),new_sw_state(i));
        max_arry(i)<='1';
        end generate;


end rtl;