| ??? 07/07/06 17:09 Read: times |
#119827 - True, but... Responding to: ???'s previous message |
Oleg said:
First of all, shift registers require clean and strong (read: not slew and not bouncing) clock signal as well as correct timed tracing clock signal to all registers at the same time. That's true. But in critical applications you can delay the serial output to be cascaded by a simple low pass filter (1k + 47p, for instance) to easily fullfill the timing requirements. Oleg said:
till you do not use phase-inverted clock of last-bit shift ones Like with 4094... Oleg said:
Another hidden contro is that if your peripheral is placed around of PCB (for example, 4 relays` group at one side and others - at another side) so your data shift line should cross around PCB what is not good due both noice and long trace handwork). In such cases and when bread boarding is used good old CMOS4000 series could be used. Abhishek could use the following scheme then: 
40106 drivers reduce the source impedance of ports, which otherwise would be too high when emitting high state. Settling time of data at serial output of 4021 is about 350nsec. Enough Erik? Toggling Px,u from high to low and from low to high again will latch the parallel input data into the 4021. Toggling Px,v from high to low and from low to high again will shift the serial data by one bit. New data can be read at Px,w after the low to high transition at Px,v. (Take care, the first bit needs no shift before being read.) Kai |
