If you think I'm crazy, ... well ... you're not the first, and I've survived so far.

However, you frequently go off pontificating about things you clearly don't understand at all and THIS thread is a good example.

First of all, the 805x doesn't support I/O mapped anything. I/O mapping implies I/O reference instructions, of which the 805x architecture has NONE. As I've tried to explain to you in the past, the closest that 805x-cores get to I/O space is the SFR's, which, of course, are accessed via direct memory reference instructions.

Memory-mapped I/O can be created by means of the external memory bus, using external-memory reference instructions. The use of these instructions will cause the low address byte and data to be multiplexed on P0, and the high address byte to appear on P2. Capturing the low address byte in an external transparent latch e.g. 74xx573 or '373 will do that job nicely. The data bus is steered and enabled by nWR, nRD, and nPSEN, in syncrhonization with P0.

In order to capitalize on this mechanism, all external memory and peripheral devices of any sort must comply with the timing requirements imposed by the MCU's system clock.

As we've agreed, this imposes limitations on the operating frequency of MCU's capable of clock rates that make the use of some peripheral devices impracticable.

However, by discrete manipulation of port pins, it is possible to create an external data bus that operates at a rate compatible with nearly any external memory or peripheral. This involves using one set of 8 bit ports as a data bus and another few pins, as many as 6 of them, to produce nRD, nWR, and the required chip-selects to the devices in question. Since firmware controls the sense and duration of these signals any timing achievable with the system clock in use in the MCU can be applied. Since access to these port pins is controlled within the confines of the internal memory-mapped architecture and instruction set of the 805x, and since no external memory reference instructions are used, the built-in signals nWR, nRD, and nPSEN do not come into play, and no implied timing relationship between the access to the external device and P0 and the signals nWR, nRD, and nPSEN. I guess you could call this method "byte-banging" as it works in the same way as bit-banging.

I'm disappointed that you don't grasp this fundamental 805x concept. I suppose it's because you've been using those all-in-one, self-contained single-chippers for so long you've forgotten what it's like to use something not built into your MCU. It's just sad ... <sigh> ...

RE