??? 10/18/06 14:14 Read: times |
#126658 - FPGA/CPLD drawbacks Responding to: ???'s previous message |
Richard Erlacher said:
Trading off board space and cost between the SSI/MSI vs. CPLD's, these days, the CPLD always wins out. A 36 MC CPLD costs But there are also many points, where the CMOS logic always wins out: 1. CPLD,FPGA are often only 3.3V or below, CMOS can work with 5V, 12V or 15V. E.g. for 15V you need only a level converter CD4504 for the serial bus and some CD4094 for the outputs and CD4021 for the inputs. 2. placing a common serial bus and some CMOS circuits exact on this place, where the IOs are needed may cause an easier pcb as a single big FPGA in the middle of the pcb and tons of wires around it. 3. FPGA need often more current as CMOS logic circuits. Peter |