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???
02/02/07 08:30
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Msg Score: +1
 +1 Good Answer/Helpful		 #131916 - now THIS is a BAD documentation
Responding to: ???'s previous message
K.ganeshan said:

Extract from Datasheet:

Active-LOW reset. On-chip power-on reset allows operation without external reset
components. A reset counter and reset glitch suppression circuitry prevent spurious
and incomplete resets.

Great.
However, there is no single line on external reset requirements.

K.ganeshan said:
Only power and ground connections are required to operate the P89LPC932A1 when
internal reset option is selected.


The web is full of cries of those who relied on the internal reset of LPC9xx and did not read all those small letters... The internal reset does not work reliably if VCC does not get below 0.2V... This is as bad as telling "RC reset is OK if VCC slew is better than xxxV/ms"...

JW

PS. There are a few hints, though. In the characteristics in datasheet is a mention of the glitch rejection on /RST pin; and IMHO more importantly, the ISP entry diagram states a minimum of 50us between VCC rampup and /RST release, which I would take at least as a rough guide to determine the /RST pulse requirement. There is no guarantee in it though and NXP does a bad service for developers by (sometimes deliberately) omitting a lot of vital information from the datasheets...




List of 39 messages in thread
TopicAuthorDate
min reset width?            01/01/70 00:00      
   WHY            01/01/70 00:00      
      why?            01/01/70 00:00      
      Which reset chip, and how long a pulse?            01/01/70 00:00      
      "proper supervisor"?            01/01/70 00:00      
         so why ...            01/01/70 00:00      
            Data Sheet vs User Manual            01/01/70 00:00      
               Data Sheet vs User Manual            01/01/70 00:00      
               wherizit?            01/01/70 00:00      
                  Which uP are you looking at?            01/01/70 00:00      
                     P89LPC932A1            01/01/70 00:00      
                        Hey! Where'd you get Rev 2?            01/01/70 00:00      
                           That's it: I said, it is not in the datasheet/UM!            01/01/70 00:00      
                              Webmaster? They have a webmaster?            01/01/70 00:00      
         Only at 5V...            01/01/70 00:00      
         words, words            01/01/70 00:00      
   Does it not have an internal Reset circuit?            01/01/70 00:00      
      now THIS is a BAD documentation            01/01/70 00:00      
         Does it imply            01/01/70 00:00      
            infernal reset (not a typo!)            01/01/70 00:00      
               So, what's the "right" way?            01/01/70 00:00      
                  don't use it as a port pin            01/01/70 00:00      
                     It's not a pitty but a shame!            01/01/70 00:00      
                        it's "creeping feature"-ism            01/01/70 00:00      
                           not a waste            01/01/70 00:00      
         Yes, I remember those many complaints!!            01/01/70 00:00      
         And what about...            01/01/70 00:00      
            internally timed            01/01/70 00:00      
               I LOVE it            01/01/70 00:00      
                  OK so let's vote            01/01/70 00:00      
                     no voting, please            01/01/70 00:00      
                        this is not taste, but facts            01/01/70 00:00      
   So, how's one supposed to reset this thing?            01/01/70 00:00      
   lets see...            01/01/70 00:00      
      Yes, but what's REQUIRED?            01/01/70 00:00      
   Some results            01/01/70 00:00      
      with or without the reset chip?            01/01/70 00:00      
         now with the reset chips            01/01/70 00:00      
            and the troubles were BEFORE or AFTER?            01/01/70 00:00      

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