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???
02/02/07 16:33
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 		 #131930 - And what about...
Responding to: ???'s previous message
Jan said:
PS. There are a few hints, though. In the characteristics in datasheet is a mention of the glitch rejection on /RST pin; and IMHO more importantly, the ISP entry diagram states a minimum of 50us between VCC rampup and /RST release, which I would take at least as a rough guide to determine the /RST pulse requirement.

And what about the start-up time of oscillator? If the Pierce oscillator is used a minimum reset delay of 10msec should be provided. But take note that Intel's standard RC-reset circuitry offers about 100msec delay between (instantaneous assumed) power-up and release of reset signal! Poor crystals and unsane temperatures can cause large start-up times...

Kai

List of 39 messages in thread
TopicAuthorDate
min reset width?            01/01/70 00:00      
   WHY            01/01/70 00:00      
      why?            01/01/70 00:00      
      Which reset chip, and how long a pulse?            01/01/70 00:00      
      "proper supervisor"?            01/01/70 00:00      
         so why ...            01/01/70 00:00      
            Data Sheet vs User Manual            01/01/70 00:00      
               Data Sheet vs User Manual            01/01/70 00:00      
               wherizit?            01/01/70 00:00      
                  Which uP are you looking at?            01/01/70 00:00      
                     P89LPC932A1            01/01/70 00:00      
                        Hey! Where'd you get Rev 2?            01/01/70 00:00      
                           That's it: I said, it is not in the datasheet/UM!            01/01/70 00:00      
                              Webmaster? They have a webmaster?            01/01/70 00:00      
         Only at 5V...            01/01/70 00:00      
         words, words            01/01/70 00:00      
   Does it not have an internal Reset circuit?            01/01/70 00:00      
      now THIS is a BAD documentation            01/01/70 00:00      
         Does it imply            01/01/70 00:00      
            infernal reset (not a typo!)            01/01/70 00:00      
               So, what's the "right" way?            01/01/70 00:00      
                  don't use it as a port pin            01/01/70 00:00      
                     It's not a pitty but a shame!            01/01/70 00:00      
                        it's "creeping feature"-ism            01/01/70 00:00      
                           not a waste            01/01/70 00:00      
         Yes, I remember those many complaints!!            01/01/70 00:00      
         And what about...            01/01/70 00:00      
            internally timed            01/01/70 00:00      
               I LOVE it            01/01/70 00:00      
                  OK so let's vote            01/01/70 00:00      
                     no voting, please            01/01/70 00:00      
                        this is not taste, but facts            01/01/70 00:00      
   So, how's one supposed to reset this thing?            01/01/70 00:00      
   lets see...            01/01/70 00:00      
      Yes, but what's REQUIRED?            01/01/70 00:00      
   Some results            01/01/70 00:00      
      with or without the reset chip?            01/01/70 00:00      
         now with the reset chips            01/01/70 00:00      
            and the troubles were BEFORE or AFTER?            01/01/70 00:00      

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