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???
02/02/07 18:15
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 		 #131933 - internally timed
Responding to: ???'s previous message
I'd say that the ICP/ISP entry is internally timed from the internal RC oscillator - which might have a fast enough startup. Hence reset might be synchronous but independent on the crystal oscillator.

I don't have the datasheet on hand at the moment but this might have to do with the method how the crystal oscillator takes over from the internal oscillator.
If it's not specified exactly in the datasheet, that's an another issue which has to be clarified by NXP...

JW

PS That the datasheet does not contain vital information is too bad, but I hate more the fact, that for the full picture one has to read TWO documents, one containing some 80% of information of the other and vice versa...



List of 39 messages in thread
TopicAuthorDate
min reset width?            01/01/70 00:00      
   WHY            01/01/70 00:00      
      why?            01/01/70 00:00      
      Which reset chip, and how long a pulse?            01/01/70 00:00      
      "proper supervisor"?            01/01/70 00:00      
         so why ...            01/01/70 00:00      
            Data Sheet vs User Manual            01/01/70 00:00      
               Data Sheet vs User Manual            01/01/70 00:00      
               wherizit?            01/01/70 00:00      
                  Which uP are you looking at?            01/01/70 00:00      
                     P89LPC932A1            01/01/70 00:00      
                        Hey! Where'd you get Rev 2?            01/01/70 00:00      
                           That's it: I said, it is not in the datasheet/UM!            01/01/70 00:00      
                              Webmaster? They have a webmaster?            01/01/70 00:00      
         Only at 5V...            01/01/70 00:00      
         words, words            01/01/70 00:00      
   Does it not have an internal Reset circuit?            01/01/70 00:00      
      now THIS is a BAD documentation            01/01/70 00:00      
         Does it imply            01/01/70 00:00      
            infernal reset (not a typo!)            01/01/70 00:00      
               So, what's the "right" way?            01/01/70 00:00      
                  don't use it as a port pin            01/01/70 00:00      
                     It's not a pitty but a shame!            01/01/70 00:00      
                        it's "creeping feature"-ism            01/01/70 00:00      
                           not a waste            01/01/70 00:00      
         Yes, I remember those many complaints!!            01/01/70 00:00      
         And what about...            01/01/70 00:00      
            internally timed            01/01/70 00:00      
               I LOVE it            01/01/70 00:00      
                  OK so let's vote            01/01/70 00:00      
                     no voting, please            01/01/70 00:00      
                        this is not taste, but facts            01/01/70 00:00      
   So, how's one supposed to reset this thing?            01/01/70 00:00      
   lets see...            01/01/70 00:00      
      Yes, but what's REQUIRED?            01/01/70 00:00      
   Some results            01/01/70 00:00      
      with or without the reset chip?            01/01/70 00:00      
         now with the reset chips            01/01/70 00:00      
            and the troubles were BEFORE or AFTER?            01/01/70 00:00      

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