Mikkel:
Most certainly the problem you are experiencing is one with the way you generate the WRITE/ pulse for the FIFO. You indicated that you use the RCO output of the 74HC163 counter as the WRITE pulse. You should get TI's data sheet for the counter and look closely at the "equivalent" logic for the HC163.

When you study carefully you will notice that the RCO is a logical combination of the ENT, QA, QB, QC, and QD pins. As such, even though this counter is a synchronous counter, there is a likelyhood of there being a narrow glitch on the RCO output just at the time the counter bits are changing. Not all the flip-flops will change at exactly the same time, particularly at the instance of some small noise spike on the power or ground lines.

As Jez commented the FIFOs are VERY VERY sensitive to noise and glitches on their control lines.....particularly in the more modern day ulta-fast FIFOs. A glitch on the RCO line could very easily propagate right into the FIFO and screw up the internal position pointer in the FIFO even putting it into a metastable state.

One suggestion to "fix" this problem is to buffer the RCO output of the counter through a D type flipflop. One choice would be to clock the D flipflop on the opposite edge of the clocking signal that what increments the counter. This will have the effect of delaying the RCO pulse by 1/2 of a clock time (supposing that the clocking wavform has a 50% duty cycle). The other method is to select a D flip flip that has a hold time of D input from clock edge of either zero nanoseconds (or a hold time that is less than the MINUMUM clock to output delay of the counter). Using this scheme you clock the D flipflop on the same edge as the counter clock and the net pulse out of the flio flop is delayed by one clock time from the RCO pin.

Michael Karas