OK....I looked at your schematic snippet. I can suggest that you should buffer the clock signal coming from the header through a schmidt trigger type buffer. The shift register and counter are going to be susceptable to noise on the clocking line coming from the cable. Noise or ringing due to the cable will advance the counters and shifters more often than they should be triggered.

It would also be a very good idea to trigger the 'HC4538 off the same signal that generates the RCLK for the shift registers. This way a false trigger of the 'HC4538 is less likely to generate extra write pulses to the FIFO when they are not intended.

As I mentioned before the RCO output can experience glitches whenever the counter changes count. You would also do well to look at changing the clocking gating of the RCLK generator. The possible glitches on RCO occur right after the rising edge of the clock and you have the RCLK generator gate enabled right at this time as the same CLK signal, from the connector, has gone high, Why dont you consider generating the RCLK and 'HC4538 trigger off the opposite edge of the clock signal coming from the header?

Michael Karas