| ??? 01/17/04 00:25 Read: times |
#62759 - RE: FIFO problem Responding to: ???'s previous message |
Erik & Mikkel:
When using a series back match resistor in a signal line to minimize ringing it is supposed to go as close to the low impedance generator gate output as possible. So...Mikkel you guessed correct and Erik has it incorrect. Michael Karas Mikkel: I really think you need to evaluate the timing in the circuit FIRST. If you patch and patch and patch you may make the problem hit rate reduce to the point that you "think" you have it fixed. However I really feel that you have issues with that RCO output of the counter. I learned the hard way a LONG LONG time ago that you NEVER use a RCO output of your type of counter as a clock or strobe to edge sensitive logic without properly gating or synchronizing the signal to mask its glitch potential time zone. Michael Karas |
| Topic | Author | Date |
| FIFO problem | 01/01/70 00:00 | |
| RE: FIFO problem | 01/01/70 00:00 | |
| RE: FIFO problem | 01/01/70 00:00 | |
| RE: FIFO problem | 01/01/70 00:00 | |
| RE: FIFO problem | 01/01/70 00:00 | |
| RE: FIFO problem | 01/01/70 00:00 | |
| RE: FIFO problem | 01/01/70 00:00 | |
RE: FIFO problem | 01/01/70 00:00 | |
| RE: FIFO problem | 01/01/70 00:00 | |
| RE: FIFO problem | 01/01/70 00:00 | |
| RE: FIFO problem | 01/01/70 00:00 | |
| RE: FIFO problem | 01/01/70 00:00 | |
| RE: FIFO problem | 01/01/70 00:00 | |
| RE: FIFO problem | 01/01/70 00:00 | |
| RE: FIFO problem | 01/01/70 00:00 | |
| RE: FIFO problem | 01/01/70 00:00 |