Michael Karas wrote:
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It would also be a very good idea to trigger the 'HC4538 off the same signal that generates the RCLK for the shift registers. This way a false trigger of the 'HC4538 is less likely to generate extra write pulses to the FIFO when they are not intended.

As I mentioned before the RCO output can experience glitches whenever the counter changes count. You would also do well to look at changing the clocking gating of the RCLK generator. The possible glitches on RCO occur right after the rising edge of the clock and you have the RCLK generator gate enabled right at this time as the same CLK signal, from the connector, has gone high, Why dont you consider generating the RCLK and 'HC4538 trigger off the opposite edge of the clock signal coming from the header?

I have had a look at your suggestions, and I (think I) have come up with a possible solution...

I will add a HC14 at the input as you suggested (two gates per. signal). I will then replace the clock input on the RCLK NAND gate, with an inverted clock signal. Then I should get an output pulse during the second half of the RCO pulse. As that pulse may be too late (another byte is starting to enter the shift register), I could use the leading edge of the new pulse to trigger the other half of the 4538 chip. That way the two registers should store the data around the middle of the RCO pulse. And the first half of the RCO pulse (where the glitches should occur) is unused.

I could then trigger the existing 4538 off the trailing edge of the RCLK pulse, to take care of the first problem mentioned above.

If this sounds reasonable I could solve the problem without adding more parts (except for the HC14) to the already crowded PCB...

I have drawn up a small schematic showing the new and old RCLK circuit here:

http://stiftsbogtrykkeriet.dk/~mcs/FIFO2.gif

Best regards,

Mikkel C. Simonsen