Anyway of you really want some data on simm modules then a simple google search brings up over 50,000 hits which should give a good idea of dram structure and the problems of working with it.Reading the data sheets you will see that the problem with interfacing the 8051 to dram is hiding the refresh cycles,and for syncronous dynamic ram actually translating the simple 8052 read and write cycles into the much more complex read and write cycles needed.I suppose it would be possible to interface the 8-52 to dram using a cpld to handle the interface but probaby more trouble than its worth,I should stick to flash.