Right now, I am in the deciding phase of a project. I need to have 4MB of battery backed up RAM on board. I do not know if the DRAM can be maintained by a CPLD while the CPU is off / sleeping. And what about the power consumption in the backup state?
The power consumption is about the same DRAM was never intended for backup.
I am looking at the possibility of using 1MB/2MB SRAMs to achieve this.
MB bit or byte? if byte, that would be a possibility
BTW : the 4MB ram I need should work as fast as an interface to a standard SRAM.
Read AND write or would "as fast as" for read and a slower write be acceptable.
Problem with paging is to find out the boundaries and switch pages. This consumes processor time.
If you use a Philips Mx or 669 no paging necessary, ST and Dallas, I believe, also have extended address '51 derivatives.
I have seen an article interfacing a 256x1 DRAM to the PIC. Is something similar possible for the 8051?
possible, yes, practical, no

Erik