Jez

You said: <
I have looked at using some of the odd edo ram sticks in my junk box with some suitable cpld to provide the interface timing,its not difficult to do it just wether anyone would seriously use it.
If anyone does have an application which warrents it I could knock something up in a few days which wouldlook like a standard static ram interface to the 8052 but work with edo ram for example >


Right now, I am in the deciding phase of a project. I need to have 4MB of battery backed up RAM on board. I do not know if the DRAM can be maintained by a CPLD while the CPU is off / sleeping. And what about the power consumption in the backup state?

I am looking at the possibility of using 1MB/2MB SRAMs to achieve this.

Can you please comment on the possibilities for implementation.

BTW : the 4MB ram I need should work as fast as an interface to a standard SRAM. Problem with paging is to find out the boundaries and switch pages. This consumes processor time.

I have seen an article interfacing a 256x1 DRAM to the PIC. Is something similar possible for the 8051?

Jerson