As I understand it, Verilog and VHDL are both Hardware Description Languages (HDLs).
This is analoguous to the many different languages available for writing software; eg, 'C' and Pascal are both software programming languages. Which one you choose depends on available tools, expertise, support, history, personal preference, etc,...

I'm sure you can mix them - but why make like complicated for yourself?
I think the only reason to do so would be if you had to integrate components that really weren't available in the "preferred" language.

(yes, I have done software projects in a mixture of 'C' and Pascal)