Metastability can happen when you don't meet the setup and hold times for the input of a flip/flop. Sometimes the flip/flop doesn't know to flip or flop and just oscillates and fall one way or another - not good. Normally associated with CPLDS and FPGAs as these are high speed devices with flip/flops! If you have an external input to a CPLD/FPGA (or flip/flop) that is not synchronised to the clock used for the logic device, you may have a problem. There are ways around this - see xilinx.com/altera.com for discussions on this. Be aware of this problem as it will bite you when you least expect it even on low speed circuits.


Also, for the gentleman that was using the 95108 cPLD - you'll need a much much bigger device if you want to implement a cpu- and a crash course on cpu design and fpgas!

Cheers