Hi,

Consider the /CE signal of an SRAM(70ns e.g.) connected to 89C52 @ 11.0592 MHz. An XC9572 is used as address decoder. Now, the /CE signal comming from CPLD is fed to a MAX691A and the /CEout of 691A to /CE of SRAM. Considering the maximum -not typical- delays (as recommended by Eric) we have a 15ns for the CPLD (faster one's not found here) and 10ns for 691A, a total of 25ns. My 1st question is that how exactly I may calculate the allowed time delay. I know it has something to do with the timing diagrams, but the calculation procedure is what I don't know. The 2nd question is about similar timing calculation for the LE signals to HC573s in my parallel scheme (which is of some social leper). These LE signals are made by the CPLD so they should have some 15ns delay, on the other hand the parallel data to be fed to these latches passes through an HC245 (some isolation of uC from outgoing flat cables) and this HC245 adds some delay to AD0..AD7 lines. I doubt whether or not this delay might cause something like having the LE pulses applied to HC573s prior to having valid data on their input or maybe too late LE signal because of longer delay for LE signals to be produced by a 5x32 decoder implemented in the CPLD. Yet I don't know how to calculate the timings. 3rd qeuestion: MAX691 datasheet orders to connect PFI to GND or Vout if it's not used, but I see circuits that have simply left the pin floating. Why?

Best.