Payam, only now have you given us sufficient information in order to give a reasonable reply.

Rather than give you the exact solution - I'll give you some hints.

For the ram we need to consider two bus cycles - read and write.
For read we have the /RD signal - the spec sheet will give you the low width or the formula for this width in relation to the clock rate. Ideally we want the address to be stable before we activate the /CS on the ram chip - so add up your delays in the address path. From the falling edge of /RD we have a fixed amount of time to read the data from the ram chip - this consists of delays in the /CS path + access time of the ram chip + data path delays + data read setup time : these should add up to less than the /RD width. Put another way, the 89c51 has to see stable data on it's pins + the read data setup time before /RD goes high. There's also a read data hold spec - this means the data must remain stable for the required time before it changes.

For the write, the address must be stable before /WR and /CS goes low. In many cases we also want the data to be stable. So we have a /WR signal width spec that determines the time. Again we have the /CS path delay from /WR and the data hold time. We have the data path delay and the write time of the ram chip.

For your latches we have the data path time and the LE time. The problem with using latches is that if your LE is high and your data is changing - the outputs will also change giving the possiblility of glitches - so you must ensure that your data is stable when LE goes high and stays stable until LE falls. The critical parameters are the data hold time after LE falls and the LE width.

With the address decoding, you need to make sure that the address cannot change after /RD or /WR have gone low - so you need to make sure your buffer delays etc do not violate this.

So read your data sheets carefully, use worst case values and never violate your setup and hold times. Hopefully this information will help you solve your problem.