| ??? 02/06/05 08:06 Read: times Msg Score: +1 +1 Good Answer/Helpful |
#86644 - timing diagrams Responding to: ???'s previous message |
Payam Soltany said:
My 1st question is that how exactly I may calculate the allowed time delay. I know it has something to do with the timing diagrams, but the calculation procedure is what I don't know. You really need to draw a timing diagram. Get some graph paper. In a column on the left, write the name of each signal, starting with the first input, and work your way down to the last output, in order. Then draw all of the inputs. Then figure out the logic and draw the intermediate signals (between latches and buffers, for example), then draw the outputs. Do it exactly like you'd want to see it in a data book or on a logic analyzer display. -a |
| Topic | Author | Date |
| /CE propagaion delay in MAX691 | 01/01/70 00:00 | |
| Prop delay in max691 | 01/01/70 00:00 | |
| Batteries | 01/01/70 00:00 | |
| or check out the FLASH+RAM combination | 01/01/70 00:00 | |
| FRAM | 01/01/70 00:00 | |
| another option | 01/01/70 00:00 | |
| ZMD | 01/01/70 00:00 | |
| that's the one | 01/01/70 00:00 | |
| MAX691+battery | 01/01/70 00:00 | |
| what is the problem | 01/01/70 00:00 | |
| How can that be off topic | 01/01/70 00:00 | |
| the matter | 01/01/70 00:00 | |
| It's definitely on-topic! | 01/01/70 00:00 | |
| NEVER design with typicals | 01/01/70 00:00 | |
| MAX691 versus MAX691A, leakage currents | 01/01/70 00:00 | |
| take note, Kai is using the right value | 01/01/70 00:00 | |
| MAX691A | 01/01/70 00:00 | |
| EEPROM | 01/01/70 00:00 | |
| EEprom | 01/01/70 00:00 | |
| And..... | 01/01/70 00:00 | |
| more Qs on /CE | 01/01/70 00:00 | |
| This is more like a valid question | 01/01/70 00:00 | |
timing diagrams | 01/01/70 00:00 |