hi,



Well, as about clock. Multiplifier CPLD realization may or may not require a clock. When clock is not involved then synthesis implements the function with pure logic - just a cascade of summators with many carryes expansions. It all results with huge logic and slow result time.
When clock is utilized then process is implemented using pipeline, i.e. "shift-[hold]-sum" method. It may or may not increase the logic cells usage but surely decreases the time of result. Indeed, the result time is very depended on clock frequency then. It is because all pipeline stages are changed with clock ratio. So when clock is slow then you may not obtain good time anyway.
For example, classic device MAX7000 does produce result for 10x10bit function for about 80ns after last data has been set when clock is not used.
When pipeline is used then even 1-clock pipeline decreases this time to 40ns. But you should add 1 clock time due one pipeline stage. So if you use 12MHz clock then total time will be 40+83 ~= 120ns. And as you may see, the total time is increased. But if clock is 50MHz then total time is only 40+20=60ns. Two stages pipeline decreases time yet more to about 20ns. But it starts to increase number of logic cell used and total time is still the same: 20+(20*2)=60ns.

As about cost. Classic MAX7000 device is not suitable for such task. For 10x10bit function it requires EPM7256 device. Here they cost about 30..80 USD depend on package and speed. Moreover they will be about 100% utilized and you will not be able to add in it some more additional things you usualy need with.
When we come to configurable CPLD like Altera Acex then EM1K10 may be used. This device costs about 10 USD here. And 10x10bit function "eats" only 30% of logic cells. But the problem is that this device SRAM-based, so you need to upload its hardware configuration at each power-up with either special IC or your MCU. Another trouble is that these devices are two-power ones and require both 3.3V and 2.5V supply.

So what I may suggest:
- if you need with speed and do not think about money very much then use SiLabs F120 with MAC built-in.
- if you do complex board with many hardware then CPLD may be utilized for MUL and many other tasks as well.
For example, my current project utilizes both SiLabs F120 and Acex EP1K50 CPLD. But it is really huge: many interfaces (RAMs, DataFlashes, MMC, FRAM, RTC, VGA, stereo-sound, Network and rest...). The cost of such board is planed for about 300 USD so we decide to use CPLD for VGA,DMA and many other things. As result we decrease additional hardware and a couple of small ICs over the board space. From other side, such board uses huge CPLD in QFP208 package and even now it is only 60% utilized.

Regards,
Oleg