hi,


I do not know what you mean with it but Altera LPM_MULT description says clean:

Port name: clock
The clock port provides pipelined operation for the lpm_mult function. For LPM_PIPELINE values other than 0 (default value), the clock port must be connected.

Parameter: LPM_PIPELINE
Specifies the number of Clock cycles of latency associated with the result[] output. A value of zero (0) indicates that no latency exists, and that a purely combinatorial function will be instantiated. If omitted, the default is 0 (non-pipelined).

So what I said: if no clock is used for a multiplier then it is realized as pure cascade summators without pipeline. If clock is enabled for LPM_MULT then synthesis implements pipelined mult function. What is wrong, please?


Indeed, it "eats" just EPM7256. See below.


Why not? Multiple Array Matrix (MAX) devices are high-performance solutions for a broad array of applications (it is what Altera says on their site). They are not marked as "not recommended for a new design". Moreover, these devices are instant-on and non-volatile and this fact of matter is very useful in some tasks where user needs that CPLD must be ready-to-use immediatelly after power-on.
So, maybe some people do not use these devices but I would not say "nobody".



Depend what you mean saing "is not slow". For example, here we need to multiplicate RGB (8+8+8bits) with alpha-channel (bright) coefficients (8-bit) for the each dot which then comes out from CPLD to DAC. So we use three LPM_MULT each as 8x8 bits.
Pure LPM_MULT without clock of Acex EP1K50 does 8x8 bits for about 40ns. Here I say: when the valid data comes to LPM_MULT input lines then the valid result is obtained after 40ns on its output lines. Once again: no clock is used.
Then we switch LMP_MULT to pipelined mode. We connect clock 70MHz to it and set LPM_PIPELINE to 3. First clock locks input data into LMP_MULT pipeline and after third clock the valid result appears on its output lines. 70MHz is ~14ns clock period. 14ns is between 1st and 2nd clock + 14ns is between 2nd and 3rd clock + about 7ns is LMP_MULT output register delay. Now the valid result appears on LPM_MULT output lines after about 35ns from 1st clock. Could you say what is the rubbish you mentioned about?
And other question: from where do you obtain 70MHz (or even 35 for PLL) in system where only 12MHz crystal is used for MCU?



Okay, okay, just relax this saturday.

Regards,
Oleg