You have take what Altera say with a pinch of salt their 7000 series cplds are old and power hungry there are many newer ones which are far better and much cheaper.
You are correct in what you say about the altera multiplier macro but in general vhdl does not infer a pipelined multiplier if you use a clock.its just that the design tools infer the altera macro if you let them and that just what altera does,in fact you can stop the altera software from infering any macros at all and force it to implment all the logic from scratch.
Anyway I am just in the process of writing a little memory mapped multiplier because i am just too wonderous for my own good sometimes :)