Well, as about clock. Multiplifier CPLD realization may or may not require a clock. When clock is not involved then synthesis implements the function with pure logic - just a cascade of summators with many carryes expansions. It all results with huge logic and slow result time.
When clock is utilized then process is implemented using pipeline, i.e. "shift-[hold]-sum" method. It may or may not increase the logic cells usage but surely decreases the time of result. Indeed, the result time is very depended on clock frequency then. It is because all pipeline stages are changed with clock ratio. So when clock is slow then you may not obtain good time anyway.


Can we just clear something up? what you are saying here is rubbish

1, Using a clock for a multiplier does not infer a pipelined multiplier.
2, A 10 bit multiplier as a single block of logic is not huge as I tried to show it takes about 190 LE's
3, The resulting multiplier is not slow and certainly using a standard cpld speeds of at least 70 Mhz are easily achieved.
4, Nobody uses Altera 7000 cplds for new designs.
5, I cannot remember what other rubish you wrote something about costing $30-80
But please just stop writting stuff about things you clearly know nothing about.Its annoying it confuses the issues it doesnt help.