Your big long presentation does not prove at all how a clocked design can be faster for a single multiply than the asynchronous "crash" logic design.

On a given platform with a specific characteristic logic delay through the circuits the clocked implementation CANNOT in general be faster than the pure combinatorial design. The reason for this is because that every flip-flop element has a setup time requirement prior to clock. Crash logic does not have this limitation.

So if the problem definition is to achieve the fastest 10x10 multiply from time of presentation of inputs to availability of output it will come from the combinatorial logic design.

On the other hand if the problem definition is one of achieving the fastest RATE of producing 10x10 multiply results then the clocked design comes into play. Here the idea is to divide up the work of producing the multiply result into stages. This process, as you have so aptly indicated, is called pipelining. At each state the results of the previous state are saved in registers and then used at the next state. The process of going from state to state in your FPGA design is controlled by the clocking process. If you add more levels to a pipeline process the the job done at each level becomes simpler and can thus be done faster. There is of course a point of diminishing returns to this theory because of the universal laws of entropy. (In the FPGA of course this is rooted in the finite limit to how fast the circuits can operate). Pipelining however does take the time to fill the sequence of intermediate registers before the first result can be seen. Then as long as inputs continue to be clocked in their results will pop out N stages later. The time between the available results CAN be shorter than the time for the crash logic design thus giving the appearance of a faster multiply. BUT ONLY AFTER THE PIPELINE HAS FIRST BEEN FILLED AND YOU TAKE ADVANTAGE OF OVERLAPPING THE PIPELINE DELAY BY PRESENTING NEW DATA TO THE INPUT SIDE OF THE CIRCUIT BEFORE YOU USE THE RESULTS AT THE OUTPUT OF THE CIRCUIT.

Michael Karas