| ??? 06/19/05 19:41 Read: times |
#95303 - well Responding to: ???'s previous message |
You could do but you are starting to get into very large fpgas to be able to do that and it gets a bit expensive.Also using a 2 Ghz PC it takes about 12 hours to simulate a program running for 10 ms in modelsim when you are simualting the functional output generated by the place and route tools containing about 50,000 signals each of which has to be checked for scheduled changes on each clock edge and has to have its set-up and hold times checked.I hate to think what the simualtion times would be for two cores.As for adding jtag functionality to a fpga core its certainly doable |
| Topic | Author | Date |
| ASIC '51s and speed | 01/01/70 00:00 | |
| Zylogic? | 01/01/70 00:00 | |
| probably not | 01/01/70 00:00 | |
| why not look.. | 01/01/70 00:00 | |
| Details please? | 01/01/70 00:00 | |
| Details | 01/01/70 00:00 | |
| T51 limitations | 01/01/70 00:00 | |
| t51 limitations,not quite | 01/01/70 00:00 | |
| so running from RAM | 01/01/70 00:00 | |
| TCL and all that | 01/01/70 00:00 | |
| other case, probabl same answer | 01/01/70 00:00 | |
| very interesting! | 01/01/70 00:00 | |
| Advantages of single-chip | 01/01/70 00:00 | |
| Fundamental flaw | 01/01/70 00:00 | |
| Final thought | 01/01/70 00:00 | |
| use two | 01/01/70 00:00 | |
| better one superfast | 01/01/70 00:00 | |
| Pitfall? | 01/01/70 00:00 | |
| Multi cpu pitfalls | 01/01/70 00:00 | |
| Hardware delegation? | 01/01/70 00:00 | |
| 2 questions | 01/01/70 00:00 | |
| Why are you obsesed with zylogic? | 01/01/70 00:00 | |
| Obsessed? moi! | 01/01/70 00:00 | |
| well | 01/01/70 00:00 | |
| Thanks, but no thanks | 01/01/70 00:00 | |
| uPSD | 01/01/70 00:00 | |
| sorry, no | 01/01/70 00:00 | |
| FYI - Hitex 8051 SoC kit | 01/01/70 00:00 | |
nice, will check | 01/01/70 00:00 |