| ??? 06/20/05 08:19 Read: times |
#95321 - Details please? Responding to: ???'s previous message |
Jez,
Could you please give us some more details about that core? like, What synthesis tool and what family of fpga did you use? Is the core vendor dependant (can it be used easily on Altera?) What's the size of the core? (CLBs or slices) I won't ask about reliability since you seem to be very confident about it... Thanks! |
| Topic | Author | Date |
| ASIC '51s and speed | 01/01/70 00:00 | |
| Zylogic? | 01/01/70 00:00 | |
| probably not | 01/01/70 00:00 | |
| why not look.. | 01/01/70 00:00 | |
| Details please? | 01/01/70 00:00 | |
| Details | 01/01/70 00:00 | |
| T51 limitations | 01/01/70 00:00 | |
| t51 limitations,not quite | 01/01/70 00:00 | |
| so running from RAM | 01/01/70 00:00 | |
| TCL and all that | 01/01/70 00:00 | |
| other case, probabl same answer | 01/01/70 00:00 | |
| very interesting! | 01/01/70 00:00 | |
| Advantages of single-chip | 01/01/70 00:00 | |
| Fundamental flaw | 01/01/70 00:00 | |
| Final thought | 01/01/70 00:00 | |
| use two | 01/01/70 00:00 | |
| better one superfast | 01/01/70 00:00 | |
| Pitfall? | 01/01/70 00:00 | |
| Multi cpu pitfalls | 01/01/70 00:00 | |
| Hardware delegation? | 01/01/70 00:00 | |
| 2 questions | 01/01/70 00:00 | |
| Why are you obsesed with zylogic? | 01/01/70 00:00 | |
| Obsessed? moi! | 01/01/70 00:00 | |
| well | 01/01/70 00:00 | |
| Thanks, but no thanks | 01/01/70 00:00 | |
| uPSD | 01/01/70 00:00 | |
| sorry, no | 01/01/70 00:00 | |
| FYI - Hitex 8051 SoC kit | 01/01/70 00:00 | |
nice, will check | 01/01/70 00:00 |