| ??? 06/20/05 13:12 Read: times |
#95349 - t51 limitations,not quite Responding to: ???'s previous message |
well in the t51 the rom is part of the core and uses the embedded ram which is part of the fpga to act as the program rom. so it actualy has a three stage instruction pipeline which is being fed one instruction per clock cycle except when the pipeline is stalled by a branch or an interupt.It means that you compile the fpga each time you want to change the program.
Anyway the vast amounts of cash would all go to a good cause :) |
| Topic | Author | Date |
| ASIC '51s and speed | 01/01/70 00:00 | |
| Zylogic? | 01/01/70 00:00 | |
| probably not | 01/01/70 00:00 | |
| why not look.. | 01/01/70 00:00 | |
| Details please? | 01/01/70 00:00 | |
| Details | 01/01/70 00:00 | |
| T51 limitations | 01/01/70 00:00 | |
| t51 limitations,not quite | 01/01/70 00:00 | |
| so running from RAM | 01/01/70 00:00 | |
| TCL and all that | 01/01/70 00:00 | |
| other case, probabl same answer | 01/01/70 00:00 | |
| very interesting! | 01/01/70 00:00 | |
| Advantages of single-chip | 01/01/70 00:00 | |
| Fundamental flaw | 01/01/70 00:00 | |
| Final thought | 01/01/70 00:00 | |
| use two | 01/01/70 00:00 | |
| better one superfast | 01/01/70 00:00 | |
| Pitfall? | 01/01/70 00:00 | |
| Multi cpu pitfalls | 01/01/70 00:00 | |
| Hardware delegation? | 01/01/70 00:00 | |
| 2 questions | 01/01/70 00:00 | |
| Why are you obsesed with zylogic? | 01/01/70 00:00 | |
| Obsessed? moi! | 01/01/70 00:00 | |
| well | 01/01/70 00:00 | |
| Thanks, but no thanks | 01/01/70 00:00 | |
| uPSD | 01/01/70 00:00 | |
| sorry, no | 01/01/70 00:00 | |
| FYI - Hitex 8051 SoC kit | 01/01/70 00:00 | |
nice, will check | 01/01/70 00:00 |