??? 08/19/07 15:01 Read: times |
#143400 - Observation technique affects the outcome Responding to: ???'s previous message |
Kai Klaas said:
I would suggest to add pull-downs at inputs of battery powered CMOS-RAM. Why? Extremely low supply current consumption of these CMOS-RAMS is only valid, if input levels are either exactly 0V of Vcc, otherwise the current consumption can heavily increase! I'm persuaded that it isn't a good idea to bias nWE and nCS in the negative direction, as we don't know what the behavior of the associated logic will be as Vcc falls. Also, if one's trying to discern the behavior of the MCU or BBRAM in this context of falling Vcc, affecting the bias on addresses and data may be disadvantageous in determining the actual behaviors of these components. I'm not sure of that, but with larger resistor values, there may be less risk of losing valuable information (not the memory content, but the way in which it is altered, if at all). If you power down your digital circuit, then the unavoidable leakage currents (out or into the CMOS-RAM) can cause relevant voltage drops across the substrate pn-junction of micro or eventual protections diodes at its inputs, causing the input voltage of CMOS-RAM floating to unsanely high levels, causing an excessive supply current.
100kOhm pull-downs is enough normally. I'd guess that 1 Meg or even 10 Meg resistors would do the job. Kai Teasing out an intermittent failure such as what we're discussing is not a simple task, and I'm somewhat hesitant to bias the outcomes with added components. Wildly fluctuating power consumption is not so likely to produce the fault that is being sought out, since it's in a situation in which power is decaying anyway. From where I sit, ideally, one would attempt to produce a consistent result, either a consistent failure, or a consistent absence of one, and then try to draw valid conclusions from the circumstances. What we have encountered so far, however, is an intermittent failure that gives no hint as to its origin. RE |