| ??? 08/19/07 21:01 Read: times |
#143416 - yeah, sure Responding to: ???'s previous message |
I said:
The prudent designer won't believe his own brother, though, and double-secures the thing using the chip-select gate... Richard Erlacher said:
Just how would one do that in light of the fact (a) all the IC's are operating below their specified voltages and (b) they see different Vcc levels due to noise and other factors as power decays? The prudent engineer makes sure that NOT all ICs are operating out of the specs and the key ICs are powered properly (we are talking about battery backup now, so the /CS gate IC can/may/must be powered from the battery too); or does not use ICs at all (yeah, why not, this is only a stupid /CS gate, a well-designed circuit with a single MOSFET will do*). I said:
I'd see the NVRAM blocking level below mcu reset level more logical, though. Any decent 5V CMOS mcu should respond to the reset normally down to 3V at least. And, with some moderate design effort from the mcu manufacturer, I think it is not impossible to have perfect reset behavior down to zero. Richard said:
I'd be very interested in seeing where it says what the post-reset behavior in case of decaying Vcc is. Oh yes; as I said, you'd have to apply some real brute force to the manufacturers to say this out alout notabene put in on paper B&W. Nevertheless, I firmly believe there still ARE prudent designers in the chipmakers' teams, at least at the very deep CMOS process design and characterisation level, which still do a good job in determining how the devices do and don't work, and I have philosophed on this already: throughout the whole engineering (and not only electrical), you HAVE to rely on the results a lot of engineers achieved during the decades in that particular branch of science/art/technology/whatever. Most of them are well proven by the time passed. In this respect, it's a pity this branch develops so fast; but as I said, I personally to a great extent believe in the prudence of Intel's engineers working on the original '51 as well as their successors in the major '51 "cloner" companies. Even if the marketing and management people won't allow them to say out everything aloud. JW * Oh, yet another story, this time non-reset-related, although the symptom was "random" data loss. On a board with battery-backuped SRAM (a relatively big one for that era, 256kB, a 286-based, non-PC, embedded board that was) - we experienced ocassional data loss. The clue was, that it occured usually when the machines went up after being shut down for one reason or another for more than say an hour (this sounds logical and easy, but it was not that easy to discover this relationship, as I was not told about the downtime, they just called me with "machine threw out bad data again" - anybody doing field repairs at a not-too-knowledgeable-customer knows what I am talking about). It turned out that the /CS line was indeed gated by a transistor, and somebody dropped there a bipolar instead of the MOSFET and the bias resistor sucked out the battery in just around a hour's time... |
