Until the behavior of the MCU is well-controlled during that elusive power-down interval between when Vcc falls outside tolerable limits and when various mechanisms for mitigating risks, e.g, supervisor RESET, BBRAM write-lockout, MCU power-fail detection, etc, one can't know what the risks are.

That's what I've been complaining about all this time. With very long, slow, gradual decay of Vcc, it's quite possible that the various mechanisms overlap in their non-operation, i.e, not-yet operating. The logic driving the nWE of the BBRAM could be telling the BBRAM it's being written at a time when the MCU is out of control, yet the BBRAM hasn't yet encountered its on-board trigger to write-lock itself. This could happen either because the supervisor hasn't yet managed to stop the MCU, or, simply, because the MCU does odd things in RESET when power is decaying.

There's room for doubt, hence, room for considerable investigation. I don't think the approach of "stick in a quick fix" will solve anything here.

RE