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???
08/19/07 15:50
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#143404 - Sadly, there's no guarantee it does that!
Responding to: ???'s previous message
Jan Waclawek said:
Erik Malund said:
However, what guarantee do you have that the uC will not emit any signals when 'going dead' ?

Nobody will have any trouble to stop writing on an early power fail interrupt, but, as far as I can see, the REAL problem is "what comes out of the micro when it goes into reset".

It is exactly the purpose of reset to prevent anything coming out of micro.

If that were true, I'd likely have seen no corrupted BBRAM, methinks! The circuit I used had a supervisor. The MCU had a brownout detector that causes RESET. The BBRAM has its own protection circuitry.

The prudent designer won't believe his own brother, though, and double-secures the thing using the chip-select gate...

Just how would one do that in light of the fact (a) all the IC's are operating below their specified voltages and (b) they see different Vcc levels due to noise and other factors as power decays?

I'd see the NVRAM blocking level below mcu reset level more logical, though. Any decent 5V CMOS mcu should respond to the reset normally down to 3V at least. And, with some moderate design effort from the mcu manufacturer, I think it is not impossible to have perfect reset behavior down to zero.

I'd be very interested in seeing where it says what the post-reset behavior in case of decaying Vcc is.

JW



It may, in fact, be that the MCU power-fail-detection is set lower than the BBRAM power-fail write-lock threshold. The DS1230Y sets this level at 4.5 volts. The 1230A/B set theirs at 4.75. The DS89C4x0 datasheet says that the MCU power-fail detection is between 4.6 and 4.2 volts. At the 5% trip point, the MAX1232 supervisor detects power-fail at between 4.74 and 4.5 volts, while at the 10% trip-point, it detects it at between 4.49 and 4.25 volts. That looks to me like an invitation for confusion.

It gets even more confusing if you consider that the behavior of external logic and of these components isn't well characterized for slowly decaying Vcc.

RE

List of 39 messages in thread
TopicAuthorDate
the mysterious data loss in BBRAM            01/01/70 00:00      
   I just used the Dallas parts!            01/01/70 00:00      
      I've heard only praises to the Dallas chips, too..            01/01/70 00:00      
         I agree re Dallas            01/01/70 00:00      
            another method            01/01/70 00:00      
               I don't understand            01/01/70 00:00      
                  nah            01/01/70 00:00      
                     ... I just would expect that..            01/01/70 00:00      
                        You are absolutely right, of course!            01/01/70 00:00      
                     You should dig deep when posting here!            01/01/70 00:00      
                        nope, but ...            01/01/70 00:00      
                           But, what if your post is just wrong??            01/01/70 00:00      
                              well, it was not            01/01/70 00:00      
                                 What has this to do with Jan's application??            01/01/70 00:00      
                                    everything            01/01/70 00:00      
                                       When you use a second supervisor chip, ...            01/01/70 00:00      
                                          it does - IF            01/01/70 00:00      
                                             For occasional writes you have the FLASH            01/01/70 00:00      
                                                this depends on application, too            01/01/70 00:00      
                                                   But why??            01/01/70 00:00      
                                                      early power fail interrupt .....            01/01/70 00:00      
                                                         this is the purpose of reset            01/01/70 00:00      
                                                            Sadly, there's no guarantee it does that!            01/01/70 00:00      
                                                               ensure the same voltage on mcu and RAM/supervis            01/01/70 00:00      
                                                               yeah, sure            01/01/70 00:00      
                                                            OK, once more            01/01/70 00:00      
                                                               given a proper ground and power plane ...            01/01/70 00:00      
                                                         I have to agree ...            01/01/70 00:00      
                                             this depends on application            01/01/70 00:00      
                                             There's room for doubt ...            01/01/70 00:00      
                                       thanks            01/01/70 00:00      
                                 sounds reasonably            01/01/70 00:00      
   Pull-downs at inputs of battery powered CMOS-RAM            01/01/70 00:00      
      Observation technique affects the outcome            01/01/70 00:00      
         Some comments and two questions            01/01/70 00:00      
   Designing a pre-test environment ...            01/01/70 00:00      
      Eager to hear the results!            01/01/70 00:00      
         You'll have to be patient ...            01/01/70 00:00      
   Has anyone tried THIS?            01/01/70 00:00      

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