If you endeavor to implement your "target" in FPGA, you have to consider the limitations of the FPGA. The rest is quite arbitrary, and, therefore, quite liberating.

If you intend to produce a simulator, then you need to decide quite early on the architecture you intend to simulate, and try to discover all the details omitted from the datasheet. My own slant on this is that the latter is MUCH more difficult. For example, I've been trying to get Maxim/Dallas to provide details on the Mode0 Serial port operation in their one-clockers for over a year now, with no success.

If you target your effort at programmable logic implementation, then you can explore lots of options totally ignored, so far, by chip makers who simply license a design and go from there. For example, I've read in this forum, that the MCU strokes program memory twice in order to fetch the second byte of an instruction in case it needs it as an argument in what can then be a single-cycle execution. In an FPGA-based architecture, you can look at the next 16 bytes, if you wish, on every cycle, and use a simple two-phase clock to arbitrate between data and address arithmetic in the ALU. Few instructions need to consume more than two clock cycles, since the instructions either require a memory reference or not, and, if not, i.e, if they rely on an immediate or register argument, they can be executed in a single cycle. Furthermore, there's the assortment of instructions that can, conditionally, be executed out of order, and then, of course, you can build the multiplier as a combinatorial logic element (e.g. Wallace-tree) rather than a sequential one (Booth's algorithm).

If you're experimenting with architectures, a simulator is the ideal way to do it. Once you find an architecture that you like, by means of your 'C'-level simulation, you can implement it in programmable logic, or, at least, simulate your design, in VHDL for example, as though that were your intent, just to see how it measures up.

This should provide many pleasant hundreds of hours of amusement. Amazingly enough, it could also lead to a useful and powerful programmable logic core.

The basic 805x hardware is, in my humble opinion, largely rubbish. However, its instruction set is excellent, particularly for the purpose for which it was initially intended.

If you implement that in the latest FPGA technology, it can be accompanied by nearly any standard or custom I/O facility, and, with the cost/gate approaching nil, while performance approaches infinity, you must may well extend the life of this quite excellent instruction set into the next decade, which may go beyond what the "hard" 805x does in view of the competition from ARM.

RE