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12/26/07 18:50
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 		 #148733 - It's not that simple ...
Responding to: ???'s previous message
Well ... what I got from their support staff was, and my query is below their response ...

Hi Richard,

I think the old application note you are referring to is Xapp013.pdf.

There are some changes in the chip fabric, and the carry logic of Spartan2 hasn’t share the input with the LUT.

What I’m thinking is that your fast-multiplexer can be implemented in a SRL (made of LUT) which can be a 16:1 multiplexer in one LUT. You may refer to the doc below, and Virtex device has the similar fabric with Spartan2.

http://www.xilinx.com/support/d...app211.pdf (Figure 2)

Hope this helps!

Best Regards,

Yolanda Xu

Customer Applications Engineer

Xilinx, CSS

Technical Support Center: http://www.xilinx.com/support/c...upport.htm

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From: Richard Erlacher [mailto:<deleted>]
Sent: Tuesday, December 25, 2007 12:40 AM
To: xilinxsupport; Yolanda Xu
Subject: Re: <CASE:720494> details about using carry logic

Hi, Yolanda,

I'm looking for ways of using resources already built into the FPGA, that will help me build faster multiplexers (not multipliers) and fast counters. The carry logic seems to be the logical candidate. There's precious little documentation about useful ways of using the inherent capabilities of the fast-carry logic, as most of the published application materials are little more than marketing drivel.

Many years ago, there was an app-note regarding the use of carry logic in XC4000 series LC's for fast counters. It's that sort of thing I'm looking for, but need it applied to these more modern devices.

The normal 4:1 and 8:1 multiplexers reach across several LC's thereby compounding their prop-delay with routing delay. I'm looking for ways of using the three MUXCY primitives included in every Spartan-II LC as a multiplexer rather than simply as part of the carry logic in arithmetic applications. Surely someone, somewhere at XILINX knows something more about this than has been published in recent years.

regards,

Richard Erlacher


Quite frankly, it doesn't help, as I don't see how I'd be using the carry logic as a data selector (multiplexer). I'm just after a general description of where I can apply that carry logic and where I can't, and how to infer it when I do want to use it, together with some relevant timing data.

I'm looking at this in the context of building a general purpose ALU that has two input paths, each steered by an 8-bit-wide 10:1 (in this case) mux. If I build that, and also provide a data distributor to route the data to wherever it goes after the ALU.

In the past, I've done this with tristate resources, but, as you've pointed out, those are no longer available in current FPGA technology.

I had to send my query twice, in order to get someone to read it correctly. They didn't distinguish between multiplexers and multipliers the first time. Moreover, it's often easy for them to cite a Virtex where the feature to which they refer isn't available in the devices about which I inquired.

If, for example, I wanted to build an 805x core, but in such a way that I could exercise it in a "real" environment, I'd need to use about three dozen level shifters with Spartan-3's, while I can easily "get by" with the Spartan-II XC2S200, since it is 5-volt tolerant. The SP3 might perform better, but the SP2 would work where the SP3 probably (it might workqt 3 volts ... but ...) wouldn't. Either one would require external memory, as neither has enough internal memory to do much, and certainly not enough to provide a full testbed.

In order, for example, to make the ALU capable of handling all the 805x instructions, as well as all the address arithmetic operations, takes a pretty complex ALU, but the ALU will still be considerably faster than the muxes required to steer the datapaths. That's one reason I'm looking at higher performance muxes and counters.

RE




RE


List of 282 messages in thread
TopicAuthorDate
Let's make a '51!            01/01/70 00:00      
   ???            01/01/70 00:00      
      Maybe yes...            01/01/70 00:00      
         Still digging!            01/01/70 00:00      
            re above            01/01/70 00:00      
               digging deep            01/01/70 00:00      
                  It depends on your goal            01/01/70 00:00      
         Thanks            01/01/70 00:00      
   a simulation which actualy works            01/01/70 00:00      
      clockwise            01/01/70 00:00      
      Not Nesasarily            01/01/70 00:00      
   WHAT?            01/01/70 00:00      
      Yeah, C...            01/01/70 00:00      
   From reading the subject title...            01/01/70 00:00      
      verilog to c            01/01/70 00:00      
         FpgaC            01/01/70 00:00      
            there are more similar            01/01/70 00:00      
            re :FpgaC            01/01/70 00:00      
               it's just as with any other C...            01/01/70 00:00      
   Step1: Program Counter, code fetching...            01/01/70 00:00      
      finite state machine            01/01/70 00:00      
      Step 1 1/4: the byte counter&some more infrastruct            01/01/70 00:00      
         Step 1 1/2: first problems            01/01/70 00:00      
            Why not do this ...            01/01/70 00:00      
               reset in a dozen of ways            01/01/70 00:00      
                  It\'s really simple and stupid            01/01/70 00:00      
                     Faking out the LJMP            01/01/70 00:00      
                        You can't have it both ways ...            01/01/70 00:00      
               To IOR or not to IOR            01/01/70 00:00      
                  it's probably a logic reduction            01/01/70 00:00      
                     TRANSPARENT latch?            01/01/70 00:00      
                        Using clocked registers requires multiple clocks            01/01/70 00:00      
                        How to build an oscillator            01/01/70 00:00      
                           it's simple, but not THAT simple            01/01/70 00:00      
                              Where does the IOR belong in my picture?            01/01/70 00:00      
                                 You've got to have a complete picture.            01/01/70 00:00      
                                    Thanks            01/01/70 00:00      
                                       much depends on how you perceive it            01/01/70 00:00      
                     To IOR or not to IOR            01/01/70 00:00      
                        By all means, let\'s see what you think should work            01/01/70 00:00      
                           I don\'t know how I would do it            01/01/70 00:00      
                              Why do you think it\'s a lot of logic?            01/01/70 00:00      
                                 maybe later I will arrive to the LJMP            01/01/70 00:00      
                                    It is only one of a number of options.            01/01/70 00:00      
                  to reset or not to reset            01/01/70 00:00      
                     Not so fast, there, Pilgrim ...            01/01/70 00:00      
      Is there a picture?            01/01/70 00:00      
   Simulator            01/01/70 00:00      
      well, maybe...            01/01/70 00:00      
         The question is one of what you\'re simulating            01/01/70 00:00      
   Opportunity            01/01/70 00:00      
      How about this?            01/01/70 00:00      
         Thaks            01/01/70 00:00      
      not this time...            01/01/70 00:00      
         VHDL vs C            01/01/70 00:00      
            Where you sit (and when) determines what you see            01/01/70 00:00      
               ABEL is now available free            01/01/70 00:00      
               VHDL verbosity            01/01/70 00:00      
                  Entering everything more than once is not safety            01/01/70 00:00      
                  That\'s exactly what it is!            01/01/70 00:00      
                  on tools etc.            01/01/70 00:00      
                     You could, of course, use schematics ...            01/01/70 00:00      
   some basics from the wikiwhatever            01/01/70 00:00      
      Caution is indicated            01/01/70 00:00      
   What's your goal?            01/01/70 00:00      
   Step 2: The ticks counter (and the promised bonus)            01/01/70 00:00      
      BOTTOM-UP vs TOP-DOWN DESIGN            01/01/70 00:00      
   I am stuck            01/01/70 00:00      
      Prototype the ALU?            01/01/70 00:00      
         it's still hard            01/01/70 00:00      
            Jan, if you like \"bottom-up\" ...            01/01/70 00:00      
               I\'ve added a simulation            01/01/70 00:00      
      Maybe you should complete the design            01/01/70 00:00      
   step 2 1/2: MOVCs and JMP @A+DPTR            01/01/70 00:00      
      Design, then implement???            01/01/70 00:00      
         the gross picture            01/01/70 00:00      
            To the C hater            01/01/70 00:00      
               pictures and amusement            01/01/70 00:00      
                  it\'s probably not as amusing ...            01/01/70 00:00      
                     hummmm....            01/01/70 00:00      
                        that is what you have to explore            01/01/70 00:00      
                  ...and this isn\'t very amusing either            01/01/70 00:00      
      Well, this is YOUR game ...            01/01/70 00:00      
         the simplest way            01/01/70 00:00      
            ... there are many ways...            01/01/70 00:00      
               indeed, there are many ways ... BUT ...            01/01/70 00:00      
               re: there are many ways            01/01/70 00:00      
               re: microcoded MCU's            01/01/70 00:00      
                  not really microcoding...            01/01/70 00:00      
                     where there's a will ...            01/01/70 00:00      
                     constraints            01/01/70 00:00      
                        yes, but there's certainly a lower bound...            01/01/70 00:00      
                           lower bound?            01/01/70 00:00      
                              achievable minimum            01/01/70 00:00      
                           lower bound?            01/01/70 00:00      
                              perhaps what he means is a minimal delay            01/01/70 00:00      
   the rough picture            01/01/70 00:00      
      Now, this is YOUR project ... but ...            01/01/70 00:00      
         this is what I am talking about - relative cost            01/01/70 00:00      
            try to benefit from prior art            01/01/70 00:00      
         sorry - double post            01/01/70 00:00      
      I like the new picture            01/01/70 00:00      
         it's ugly            01/01/70 00:00      
            There is no requirement for beautiful drawings            01/01/70 00:00      
            Just sketch and scan ...            01/01/70 00:00      
               Early drawings should be ugly and disorganized.            01/01/70 00:00      
                  I'm not just being contrary, BUT ...            01/01/70 00:00      
                     maybe this is the way how a stupid programmer...            01/01/70 00:00      
                        Too much emphasis on art, not enough on science            01/01/70 00:00      
                     You ARE contrary, but we love you anyway.            01/01/70 00:00      
               is this simulation of this circuit?            01/01/70 00:00      
                  YES!            01/01/70 00:00      
               correction?            01/01/70 00:00      
                  there are certainly 254            01/01/70 00:00      
                     I may be reading something incorrectly            01/01/70 00:00      
                        whoops, double post again, sorry            01/01/70 00:00      
                        try mine            01/01/70 00:00      
                           did you notice the redundant opcodes?            01/01/70 00:00      
            If you like, you can use PAINT!            01/01/70 00:00      
               GIF            01/01/70 00:00      
                  this is not available as a default option...            01/01/70 00:00      
   detour - QR6, and how to explain my ideas...            01/01/70 00:00      
      ???            01/01/70 00:00      
         read one-by-one...            01/01/70 00:00      
            Too late!            01/01/70 00:00      
      Why the context switch?            01/01/70 00:00      
         simplicity            01/01/70 00:00      
            They're unrelated            01/01/70 00:00      
               sure they are unrelated....            01/01/70 00:00      
                  Maybe it\'s just grapho-semantics            01/01/70 00:00      
                  I'm a little confused            01/01/70 00:00      
                     this is not meant to be useful...            01/01/70 00:00      
                     Now I see!            01/01/70 00:00      
                        What's next?            01/01/70 00:00      
      MHO            01/01/70 00:00      
         Correction            01/01/70 00:00      
      One thing I missed ...            01/01/70 00:00      
         yes, and...            01/01/70 00:00      
            pre-ANSI K&R            01/01/70 00:00      
               yes, thanks            01/01/70 00:00      
            Here\'s the K&R chapter            01/01/70 00:00      
   Let\'s make a \'51 core            01/01/70 00:00      
      I like it...            01/01/70 00:00      
         The diagrams are now updated            01/01/70 00:00      
            I thought this is the case...            01/01/70 00:00      
               Bit ops, duplicated registers, and PSW            01/01/70 00:00      
                  I\'d not push SFR into \"internal memory\" at all            01/01/70 00:00      
                     Maybe yes, maybe no            01/01/70 00:00      
                        Certainly no.            01/01/70 00:00      
                           No, certainly            01/01/70 00:00      
                  careful now!            01/01/70 00:00      
                     OT: will there be cheap FPGAs?            01/01/70 00:00      
                        Check ther prices!            01/01/70 00:00      
                           the cost...            01/01/70 00:00      
                              Distributed over the cost of trillions of IC's            01/01/70 00:00      
                     Size vs. Performance            01/01/70 00:00      
                        I think you should do it your way ...            01/01/70 00:00      
                           Bad assumption on my part???            01/01/70 00:00      
                              this is how we see a RAM            01/01/70 00:00      
                                 by way of clarification            01/01/70 00:00      
                              keep instruction set and its implementation apart            01/01/70 00:00      
                                 ???            01/01/70 00:00      
                                    I see what you mean            01/01/70 00:00      
                                       I've almost got it now            01/01/70 00:00      
                                          dunno            01/01/70 00:00      
                                             Dedicated RAM vs flip-flops for SFRs            01/01/70 00:00      
                                          It should have a purpose, should it not?            01/01/70 00:00      
                                             '51 registers R2-R7 are no different...            01/01/70 00:00      
                                                BUT ... he referred only to R0 and R1 ...            01/01/70 00:00      
                                                It\'s all in the approach            01/01/70 00:00      
                                             It does have a purpose            01/01/70 00:00      
                                          Correction            01/01/70 00:00      
                                             I don't think it's impossible...            01/01/70 00:00      
                                                FPGA RAMs            01/01/70 00:00      
                                                   I think I understand that...            01/01/70 00:00      
                                                      It is probably not so easy            01/01/70 00:00      
                                                      bit-split the BRAM            01/01/70 00:00      
                           I think this horse is finally dead            01/01/70 00:00      
                              Be careful not to fool yourself            01/01/70 00:00      
                                 Nobody is fooling anybody            01/01/70 00:00      
                                    Not exactly what I was after, but helpful            01/01/70 00:00      
                                       Out of curiosity, what were you after?            01/01/70 00:00      
                                          I want to understand your approach            01/01/70 00:00      
                                    I try to keep an open mind ...            01/01/70 00:00      
                              dead horses couldn't drag me away            01/01/70 00:00      
                                 A ewe's my aunt            01/01/70 00:00      
                                    You can force the structure to be what you want            01/01/70 00:00      
                                       schematics vs HDL, round 666            01/01/70 00:00      
                                          It's about the money.            01/01/70 00:00      
                                       schematic entry            01/01/70 00:00      
      You may be surprised at how easy it is            01/01/70 00:00      
         It doesn't look too difficult yet ...            01/01/70 00:00      
            different strokes for different folks            01/01/70 00:00      
      Oops - duplicate post            01/01/70 00:00      
   My two cents .. How about Duo/Quad core 8051            01/01/70 00:00      
      Not as simple as that            01/01/70 00:00      
         Just a thought            01/01/70 00:00      
            Exactly!            01/01/70 00:00      
         It's like using a team to do a job            01/01/70 00:00      
            more troubles with multiprocessor...            01/01/70 00:00      
               8051 multi-cores            01/01/70 00:00      
                  Writing code for them would be "interesting" too            01/01/70 00:00      
                  Isn't a '51 core too expensive for this?            01/01/70 00:00      
                     \'multicore\'            01/01/70 00:00      
                        it all depends on the application            01/01/70 00:00      
                           this is not pantyhose            01/01/70 00:00      
                              sure...            01/01/70 00:00      
                     Cost of an 8051 core            01/01/70 00:00      
                        that sounds like pretty expensive to me...            01/01/70 00:00      
               efficiency will surely increase            01/01/70 00:00      
                  How can that be?            01/01/70 00:00      
                     How can that be?            01/01/70 00:00      
                     maybe not "more efficient"            01/01/70 00:00      
                        it might be clever to use a different architecture            01/01/70 00:00      
                           it always MAY be            01/01/70 00:00      
      there are other ways...            01/01/70 00:00      
      One task per CPU is good            01/01/70 00:00      
         you nailed it Russ            01/01/70 00:00      
         that is where things tend fo fall apart            01/01/70 00:00      
   New subtopic - How to initialize block RAM?            01/01/70 00:00      
      there once was a ROM primitive            01/01/70 00:00      
      Initializing BRAMs            01/01/70 00:00      
         re: Initializing BRAMs            01/01/70 00:00      
            re: Initializing RAMs            01/01/70 00:00      
   Update: How the execution unit works            01/01/70 00:00      
   Yet another Verilog question            01/01/70 00:00      
      Yet another Verilog answer            01/01/70 00:00      
         Yet another Verilog thanks            01/01/70 00:00      
            why ... ?            01/01/70 00:00      
   Yo! --- Andy ---- about those fast-carry muxes ...            01/01/70 00:00      
      fast-carry muxes            01/01/70 00:00      
         It's not that simple ...            01/01/70 00:00      
            well ... i don't know.            01/01/70 00:00      
               It depends on what they can do ...            01/01/70 00:00      
                  Now I'm confused.            01/01/70 00:00      
                     it\'s just a documentation issue            01/01/70 00:00      
   Update: Implementation is underway            01/01/70 00:00      
   Update: How to handle C, AC, and OV flags?            01/01/70 00:00      
      there are a couple of ways ...            01/01/70 00:00      
         Can you be more specific?            01/01/70 00:00      
            What I think about your project doesn't matter            01/01/70 00:00      
               Re: what you think doesn't matter            01/01/70 00:00      
                  Now ... please don\'t take this as personal ...            01/01/70 00:00      
                     Okay            01/01/70 00:00      
               if you insist on using schematic entry            01/01/70 00:00      
                  If only it were that simple            01/01/70 00:00      
      you can do it "symptomatically"... but I wouldn't            01/01/70 00:00      
         More on the flags            01/01/70 00:00      
            wrong place ... sorry!            01/01/70 00:00      
      Very ungracefully            01/01/70 00:00      
      Historically...            01/01/70 00:00      
         The key, IMHO, is in the number of data paths            01/01/70 00:00      
            ... or ...            01/01/70 00:00      
               in low production, maybe            01/01/70 00:00      
                  this depends on approach            01/01/70 00:00      
               uC prototyping using FPGAs            01/01/70 00:00      
                  what challenge?            01/01/70 00:00      
         re: Historically            01/01/70 00:00      
            the REAL learning is in what synthesis tools do            01/01/70 00:00      
               Indeed            01/01/70 00:00      
                  xilinx synthesiser and others            01/01/70 00:00      
                  tedium ... yes, that's what it is ...            01/01/70 00:00      
   Update - the core now runs on the FPGA            01/01/70 00:00      
      How much code space does it support?            01/01/70 00:00      
         Re: How much code space does it support?            01/01/70 00:00      
            How about a testbench?            01/01/70 00:00      
               Good ideas            01/01/70 00:00      
            some ideas            01/01/70 00:00      
               Please clarify            01/01/70 00:00      
                  make it vonNeumann...            01/01/70 00:00      
                     I still don\'t get it            01/01/70 00:00      
                        let's not complicate things            01/01/70 00:00      
                           Re: let's not complicate things            01/01/70 00:00      
                              I'm not sure why you'd want to do that ...            01/01/70 00:00      
                              a way how to leave problems to somebody else            01/01/70 00:00      
                                 Von Neumann            01/01/70 00:00      
                              test code            01/01/70 00:00      
                                 Thanks            01/01/70 00:00      
                        Thanks ... it\\\'s clear now            01/01/70 00:00      
      8501 self tests            01/01/70 00:00      
      Another (minor) update            01/01/70 00:00      
         you need external bus            01/01/70 00:00      

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