Well, well.

After getting my little FPGA Morse code decoder to work with an external terminal, I thought the next thing should be to make it put its output on the demo board's LCD instead of the terminal.

While it would be possible to initialize and drive the LCD with a dedicated state machine implemented directly in the FPGA, I think it would make more sense to embed a general purpose processor in the FPGA and then view the LCD and the Morse code decoder as peripheral devices. That's the approach that Xilinx took with the demo that's loaded on the demo board when you get it.

Xilinx used their PicoBlaze, of course, but that wouldn't be nearly as much fun as carrying on with what Jan started in this thread by trying to write some sort of 8051 core. Maybe that's too ambitious a project for me at this point. But maybe not. I guess there's only one way to find out. If nothing else, it should bring the cost per hour of entertainment from the Xilinx demo board way down.

So anyway, I started with the beautiful opcode charts from Jan's website and started thinking about how it all might work. After a couple of weeks and many, many, many crumpled up balls of paper, I finally got started with something that might be reasonable. There are some diagrams here, along with a mind-numbing, clock-by-clock description of how each instruction would work with the proposed hardware.

If you look at the diagrams, you'll see that there's a lot of magic implied by the block labelled "Internal Memory". I think the next step is to detail what goes on inside that box. Same thing for the ALU block, which currently hides a lot of stuff.

In case it isn't obvious, I'm an amateur at this and more than interested in any comments anybody might have about the approach.

Thanks,

-- Russ