I'm curious how you intend to learn what really is "inside" the MCU. When designing an ALU, there are numerous differences that are completely transparent to the programmer. One example would be the shift-rotate operations. These can be implemented as shift registers, or as multiplexers. How it's done has huge impact on the hardware, yet makes no difference to the outcome of such operations. In an ASIC, you can use wide gates, while FPGA offers no such option, requiring, instead, that you concatenate several 4-input structures in order to create a 1 of 16 data selector (multiplexer), just as one example.

In FPGA, with small logic cells, one is forced to use the shift-registers, as large multiplexers create a large delay burden due to the need for concatenating multiple logic cells, in order to minimize timing impact.


Public-domain IP cores of both Z80 and 650x cores exhibit about a 6:1 ratio of resource requirements. This is partly due to the implementation and partly due to the register resources included in the core. The silicon volume in the commercial device seems to differ by a ratio of about 4:1.


I believe your primary difficulties will be in (a) deciding on whether to simulate a 12/6/4/2/1-clocker and (b) figuring out what, within that choice, to simulate, as manufacturers will probably be reluctant to provide implementation details.