Keep in mind, please, that it's just as easy to set as it is to reset a bit.


Back in the bit-slice days, this was done all the time.

Routing the global reset is a pretty important feature that is well supported in most programmable logic.

Clearly, the impact of RESET is more than just to force the core into an execution of LJMP 0000H. The RESET signal has lots of important things to do, all of which are achievable using a discrete preset or clear of the affected register/hardware bits.



I'm not sure how that last concept relates to Lynn's comment, particularly in light of the RESET timing.

Keep in mind, the minimal duration of RESET is two system clock cycles.

That seems to me to be long enough to do what I previously described, and to repeat it until reset goes away, and really little more. Once that timing requirement has been satisfied, no further guarantees are required. The core accepts, synchronizes, and executes the reset strobe until it's gone. Whether it goes away in 0 additional cycles or 100K, doesn't seem to matter. The logic I suggested meets this requirement and would exhibit that behavior. If you want to generate hardware, or a simulation of it, that approximates, and therefore teaches you about, the 805x core, then you have to consider such things. Certainly there's no law forcing you to do things that way, but you should, perhaps, keep in mind that CPU design ultimately ends up as a matter of silicon by the pound, as that's what the original designers had to consider.

RE