Russ,

Chapter 2 of the XST manual has a whole section on RAM and ROM coding techniques, including a discussion of the various ways of initializing RAMs.

It should be obvious that however you initialize the RAMs, it should be a method that lets you simulate your design using your init values. This means that you don't want to use the constraint editor to enter INIT values.

I only instantiate components if that's the only way to use them in a design. (For example, you can't infer dual-port RAMs with different aspect ratios.) This means that I never use INITs.

In Verilog, there are two ways of creating a ROM. One is to literally describe it:

always @(posedge clk) begin : MyROM
    if (en)
        case (addr)
            4'b0000 : data <= 8'h02;
            4'b0001 : data <= 8'h22;
            4'b0010 : data <= 8'hdd;
               ... 
            4'b1111 : data <= 8'h0d;
        endcase
end

Note that you can expand or contract both the address and data widths as necessary, and the tools will "do the right thing." The downside of this is that to change the ROM values, you have to enter them by hand (tedious) and recompile/resynthesize.

The other way is to initialize from a file using the $readmemh task in the initial block, as noted on page 237 of the XST manual. The good news here is that the synthesis tools are smart enough to know that $readmemh in this context (assuming you follow the coding guidelines) is a RAM initializer, and they will read the specified file and use it to automagically generate the required INITs.

Now for simulation, since you never know the order in which initial and always blocks are dealt with at startup, you'll be fine as long as your always block that deals with the RAM is not triggered until after the initial block reads the file. This is reasonable as the $readmemh is scheduled at time 0 before any transitions on clk (assuming registered reads as in the example in the XST manual) occur.

How you generate the stuff in the file read by $readmemh is, of course, entirely your problem :)

Good luck,

-a