| ??? 12/19/07 07:11 Read: times |
#148492 - re: Initializing RAMs Responding to: ???'s previous message |
actually used the first method in my Morse code thing to translate dit/dah patterns into ASCII characters. In that, um, case, the synthesizer generated a wad of combinatorial logic, so I was concerned that the same coding technique wouldn't work well for a much larger ROM. Your statement that the tools will "do the right thing" is encouraging. I think you got lots of combinatorial logic because you need to fully specify every memory location. There may be other constraints, too, but if you follow the guidelines it does the right thing. As for the second method, I read lots of stuff last night saying flat out that $readmemh was a simulator-only thing and that the synthesizers wouldn't deal with it properly. Maybe that was just old information? Yes, probably old information. As features are added to the devices, the tools (and the languages) need to keep up. Since $readmemh() was a convenient mechanism for initializing memories in simulation, it was a simple matter to use it for synthesis. The Xilinx manuals are still full of old information, so be wary! For example, XST does a good job of supporting Verilog-2001 constructs and syntax but the examples are still written Verilog95-style. Even worse are the VHDL examples and their retarded templates for things like component instances. In no particular order, some Xilinx VHDL doc/example annoyances: a) They still default to using the deprecated Synopsys std_logic_arith library instead of the preferred numeric_std. b) They always include the use clause for the std_logic_arith library, even if there are no math operations in the entity! c) They still use (clk'event and clk = '1') instead of rising_edge(clk). d) etc etc etc -a |
