Lynn,

you surely meant <μ$50 per gate...(?)
These figures give us $0.75-$1.00 or maybe slightly less, per core. Plus some more gates for the on-chip debugging (it would be very hard to live without it) and the "glue" (dualportRAMs etc.)

This sounds too much for me - as Erik keeps repeating, his "discrete communication coprecessors" cost sub-$. I don't think integrating more cores will yield any edge over the discrete solution technically, so the only reason what I see for such integration is cost.

But that also means that for such a communication coprocessor, the target size is maybe in the order of 5k gates or, better, less. As I see your point of having a well known, understood, accepted, supported etc. platform such as '51, there must be ways how to achieve this without departing from '51 too much.

I think there is no need for high performance, so Richard's "hardware recycling" approach would be fully justified there. Also, it would maybe help to identify the "relative cost" of individual elements of the '51 design - e.g. MUL/DIV instructions, DA A, register banks, maybe also others - I am certain that a "communication coprocessor" might run quite well without some (many?) of these, and the development tools can be relatively easily modified for this.

This would be an entirely different optimisation than what I - and presumably also Russ - have in mind (namely, optimisation for speed). And an another very, very interesting hobby task... :-)

JW