If we see RAM as a blackbox (or a conventional IC, or as a block as implemented in FPGA), with address, data and control (OE, WE), then, no, there is no "asynchronous", bitwise access.

Of course we can go deeper and look at the construction of RAM at gate or transistor level. Of course, we can then simply draw a few lines directly from the middle of RAM array, somewhere from the flipflops involved, or even add some logic around that particular few flipflops (Richard, please, don't correct me here that they are or are not flipflops or anything else - I think this is a good expression enough for the purpose of explanation).

And, on the other hand, what I am suggesting to do with SFRs is nothing less or more than such a RAM, implemented "discretely" - I mentioned several times the address ("row") decoder and output ("column") multiplexer - plus the array of registers equals a typical RAM. Except that we now have exposed the "flipflops" and can do whatever we need to do with them, extra to their function as SRAM cells.

When it comes to implementation, in some FPGAs, there are true RAM blocks, in others, RAM is simply "built" from the field cells. In the former case, it is benefitial to "split" the "trueRAM" and SFRs. In the latter, there is no difference.

If it would be true down-to-the-gate (or -transistor) level design, true SRAM libraries are often optimised for density and perhaps also performance, so it's not worth to build them up from discrete gates. That's equivalent to the former case (Lynn or anybody other please correct me if this is nonsense).

0.02SKK (for any practical use, zero)

JW