I have finally resolved this issue to my satisfaction by running an experiment.

First, I grabbed the 64 x 8 FIFO module from my Morse code project and synthesized it as a standalone thing. The synthesizer generated a LUT-based (a.k.a. "distributed") RAM for the FIFO that used up roughly 1% of the FPGA resources.

Then I added a couple of lines of code to the module to bring just one bit from within the RAM array out for continuous availability to other logic. With that change in place, the synthesizer generated 512 individual flip flops** and a whole bunch of combinatorial logic instead of the more efficient LUT-based RAM. The FPGA utilization was about ten times bigger than before.

So, while it is possible to access individual bits within a memory array implemented on an FPGA, doing so appears to kill the chance for an efficient implementation of that memory as either a block RAM or a distributed RAM, at least with the particular Xilinx tools and Xilinx FPGA that I happen to be using. I suppose a big YMMV is in order for other tools and/or chips.

Bottom line for the 8051 core:

1. I will implement the SFRs discretely, for what are now very obvious reasons.
2. I will also implement discrete copies of (all four sets of) R0/R1, so that their outputs can be wired directly to the logic for generating @Ri style addresses. I will still do normal reads of R0/R1 from the RAM (in the same way as for R2-R7) simply because trying to read the discrete copies instead would involve additional hardware.

-- Russ

** A "sea" of flip flops, one might say, as predicted here by Andy Peters.