What happens in block RAM is in no way relevant to what happens in discrete hardware. The SFR's are discrete hardware, any portion of which can be made accessible, i.e. readable or writable, to any other part of the hardware that you deem necessary.

What I intended to get across is that the SFR's are components of the internal hardware devices, whether they're I/O or whether they're internal configuration features. They, simply put, can be addressed just as any other resource, all of which can be viewed as "memory-mapped" at the top-level, if you view the code space, data space, internal memory and external memory all as being part of a larger addressable space. Addresses are simply used to make the distinction. After all, logical memory space doesn't have to be dense.

Any bit that can be tested discretely under control of the MCU must be accessible to the hardware that determines its state, ilse it doesn't exist. It is implemented as a buffer or as a flipflop which can be directly set or reset, synchronously or asynchronously, as required. If it can be done at all, by any mechanism, then it can be done whenever you need and for whatever purpose.

Any flipflop in, say, the UART receive data shift register, is accessible to the hardware, even if there's no instruction in the MCU instruction set that says "set bit 5 in the receive data shift register of the UART," can be set or cleared by the MCU hardware. That may not be necessary, but if you decide it is, then you can do that.

Again, since you can, in your hardware implementation, clear, preset, reset, set, or evaluate any feature within the hardware, at any time, nothing disallows that. After all, it's your MCU!

RE