... except they are both conceptual, taken out of thin air.



Oh, au contraire, I pray you be critical. That's why this thread is started.


Sure, as I said, there is none, except what I've written in the subject of this post, and the desire to be able to express myself.


Although I am not happy to hear this, most probably this is what I needed to hear.



I don't quite see how could I "ware" more "hard". What I've drawn is just a step away from a regular schematics...


Well, than I really don't know how to do it.


It was the intention of the drawing to show, that the drawing itself (which is close to the actual schematics) is not enough to convey this information.


There's one thing which is maybe not common in this sort of drawings, I did not draw the actual data bus (which is the only bus in the design). I replaced it by a box with letters "DB" inside. That is certainly confusing, but I spared quite a bit of long lines, which I don't draw too well.


That is supposed to be in the description.


The clock.


The PC is a reloadable synchronous counter ('161/'163 or such). I don't care what's inside, for me it's a blackbox - as I said many times, I don't know the relative cost of the building blocks anyway, and I am sure this changes from technology to technology (74xx -> CPLD -> FPGA -> GA/SoG -> SC -> raw transistors).

It's incremented upon each and every leading edge of the clock, except when the opcode register contains a JMP instruction, when it is loaded from the JUMP register rather than incremented.


When the opcode register contains a JMP instruction, the content of JUMP register (which had to be previously set up - rather tediously) it is synchronously loaded at the leading edge of the clock.

There is no address bus. The output of PC is connected directly to the addresses of the code memory (ROM).

As it is usual in RISC, there is no stack. Upon each jump, the next address after the address containing the JMP instruction is stored in the return register. It is the responsibility of the user to read the return register and store it wherever he wants, or just ignore it. It is also the responsibility of the user to copy the return register into the jump register, if he wants to perform a return (there is no explicit return instruction, just the JMP). I promised a quintessential RISC, no complex redundant instructions, just the very rudimentary ones... :-)

Well, store any data the user might find important to store... What else would you expect from "general purpose registers"?

Whatever you want. There are 64 ALU operations to burn. I'd certainly implement addition/subtraction with/without carry, shifts and rotations (barrel shifts are not out of reach, data width is only 6 bits, the barrel shift can be performed from both sources that's 11 shifts both direction, or combinations of it), and/or/xor - well, I think we have still at least half of the available operations left... Suggest some if you want.

The basic implementation would be a 27C040 EPROM (or equivalent FLASH), that's a full matrix of 19 bit input to 8 bit output (6 data bit, carry and zero flags).


To keep the things running. The whole thing is running on a synchronous counter (the PC) and a bunch of latches, that's all.

I don't think I could draw this much better on a computer. If the operation of the thing is not clear from the drawing, the straighter lines would be of no more help...

Would a real schematics help?

JW