??? 06/21/08 16:50 Read: times |
#156089 - Seldom andonly if it is of benefit Responding to: ???'s previous message |
Kai Klaas said:
Richard, why inserting a resistor in the GND line, at all? In my opinion this is entirely useless. Usually, everything is done to decrease the impedance of GND, by using one or even more solid ground planes, additional GND pins per chip package, paralleling of ground vias, etc. Everything, to decrease ground bounce and ground noise as much as ever possible. Why the hell now introducing again GND impedances, or even inductances??? What do you hope to filter out by these impedances? I don't see any benefit, but just the opposite!! I have to agree that, if you have a contiguous low-impedance Gnd plane available, you probably never will see an opportunity to benefit from reversing the benefit of that low-impedance Gnd plane. In fact, you probably won't see very much Vcc<=>Gnd noise at all if you've provided sufficient low-value bypass caps at about 1mm from the supply pins of the IC's. If, however, your Gnd plane is segmented, connected, perhaps, with traces less than a cm wide, anything can happen. The practice I see most often is nice large Gnd pours throughout sections of the board, connected with 1mm tracks in perhaps two or three places. In such a case, the 1mm tracks are already sufficient impedance to deserve scrutiny. You can add GND impedances, if two separate parts have to be connected to another, which are not referenced to the same GND potential. Something like common mode fitering, etc. But here, you have a chip that is referenced to the one and only GND potential, with inputs referenced to the one and only GND potential. This chip even doesn't provide symmetrical inputs, which could remove GND noise. Think about fast edges hitting the chip. Additional GND impedances would only result in increased ground bounce and destroyed noise margins. Why should I ever do this?? You should never do it unless it helps. Now, this is slow (<10 Mbps) communication. Where would a fast edge come from? RS232 uses slew-rate limiting cap's to avoid that. Further, in circuits, mostly CMOS, capable of producing really fast edges, there's not enough energy to produce a large current surge across the resistance in the Gnd. There are a couple of basic rules ... applicable during the trial phase ... (1) when in doubt, leave it out ... if the benefit isn't apparent, then you needn't do it. (2) if it hurts, don't do it! ... if there are observable negative effects, you haven't got the right combination of R and C, on Vcc, at the MAX232. Remember, none of this applies to the versions that use the smaller cap's. The old original MAX232 requires a couple of 1 uF cap's which require up a fair amount of current. In most < 5-chip circuits, the MAX232 makes much more noise than all the rest of the circuitry combined. Moreover, it's low enough in frequency to have an impact and be difficult to bypass. The goal is to smooth the ripple due to the MAX232 by causing the cap's on the MAX232 side of that net resistance to see just a tiny bit of isolation, enough to cause the caps to smooth the ripple at the MAX232 side of the resistance. The result will be a smaller net current flowing through that resistance, hence, a very small net voltage offset. I've occasionally found this useful on the Gnd side only with two circuits, namely the NE555 and the MAX232. This whole matter came up with a fellow who didn't know what was causing his problem. Probably, he didn't have the resources to check to see whether he had a noise problem, so someone just suggested he consider that, and away we went. At issue is the fact that he was using the original MAX232, which collects charge from Vcc and pumps it up, drawing current from Vcc, then discharging it into Vcc, and then collects charge from GND and then dumps it into Gnd. These currents don't have to impact the global Vcc and Gnd nets. They can be kept circulating through the cap on the Vcc and Gnd terminals on the MAX232. The result is much lower current flow through the global supply nets. The result of that is lower offset voltage on those resistances. Kai |