Since most voltage regulators, but not LDO's, are simply emitter followers on darlington input stages, they can respond fairly quickly to low-output caused by changing circuit conditions, but they can't pull the voltage down.

Now, since the same voltage is flowing out the GND pin via S3 as flows in via S1, doesn't the current in GND via C4 alter this balance? Current is being dumped from C2 to C4. There is current in RL on V- as also in C4. Divergent timing throughout the chip can also shift the phase between what's happening on the charge pump and what's happening on the inverter. If all the cap's and switches were perfectly ideal, this wouldn't be, but they aren't.

If you have a nicely designed circuit as the one illustrated, on a board with a contiguous GND plane, one on which the narrowest Vcc or GND trace is 10 cm wide, it's very unlikely any increased impedance between the global GND net and MAX232 GND will be helpful, and certainly not necessary. That's particularly true if you use those nice surge-stopping ferrites.

If one hasn't got those, however, and wants to know, right now, and not tomorrow, if the MAX232 noise is what's causing the circuit to go wild, or simply not go, or whatever, a 5-10 ohm R in the GND will tell. 22 Ohms in the Vcc will probably help quite a bit by itself to limit that noise.

RE