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???
10/02/08 07:50
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#158755 - all about worst-case
Responding to: ???'s previous message
An interrupt allows the processor to do other things, and then the hardware in the processor will make it jump to the interrupt handler.

That makes it easy to do other things. But each interrupt takes time. Time to enter the interrupt handler, and time to leave it.

If you do nothing but polling, then you will have to use a super-loop like:

for (;;) {
    do_spi();
    do_other_things();
}


But you can't run the SPI faster than that your do_spi() function never misses what to do.

With just detection of the SPI slave-select signal in the main loop, you can do:

for (;;) {
    if (spi_select) run_full_spi_message();
    do_other_things();
}


As soon as the spi-select line is detected, you then reserve 100% of the processor to poll the SPI signals (clock mosi and ssel) and to generate output (miso). You will not manage to do anything else while the message is sent - until your transfer loop detects that the transfer is done and the slave-select line gets released. Then you can continue in your main loop and get any other work done.

If you have a function all dedicated to polling the SPI, then the speed of this function will decrease if you get any interrupts from any other sources (for example receiving/transmitting on the UART, or handling timer ticks etc).

So if you run a polled spi-slave code, then you must either make sure that it does not get interrupted - i.e. turning off interrupts - or you must have the master run the communication at so slow speed that the polling code will not miss a single bit even if you get any timer interrupts + uart receive interrupts + uart transmit interrupts + ...

You either design with low-enough baudrate for a worst-case scenario, or you temporarily deactivate other features to reduce the worst-case.

List of 54 messages in thread
TopicAuthorDate
SPI slave            01/01/70 00:00      
   high speed?            01/01/70 00:00      
      sory for late replay.            01/01/70 00:00      
         SPI clock            01/01/70 00:00      
            not sure..            01/01/70 00:00      
               the worst possible approach            01/01/70 00:00      
                  SPI Slave Response            01/01/70 00:00      
                     further explanation?            01/01/70 00:00      
                        Fixed speed            01/01/70 00:00      
                        SPI Timing Diagrams            01/01/70 00:00      
                           UART Mode 0 - SPI like Serial Shif register            01/01/70 00:00      
                              uhm            01/01/70 00:00      
                           to joe            01/01/70 00:00      
                  your point?            01/01/70 00:00      
                     you can't fail with software master            01/01/70 00:00      
   Unanswerable!            01/01/70 00:00      
      really?            01/01/70 00:00      
         Intended for/usable for not always identical            01/01/70 00:00      
            consideration?            01/01/70 00:00      
   Some Questions            01/01/70 00:00      
      whichever you choose            01/01/70 00:00      
         low cost?            01/01/70 00:00      
            if you do not use an interrupt            01/01/70 00:00      
               polling?            01/01/70 00:00      
                  bits/s not packet size            01/01/70 00:00      
                     speed?            01/01/70 00:00      
                        bits/s not packet size!            01/01/70 00:00      
                           500ms?            01/01/70 00:00      
                        here            01/01/70 00:00      
                           Yes - I agree            01/01/70 00:00      
                              issues            01/01/70 00:00      
                                 UART!            01/01/70 00:00      
                              Not complex - just requiring low baudrate            01/01/70 00:00      
                                 kind of rcorrect            01/01/70 00:00      
                                    Complexity contra recommendable            01/01/70 00:00      
                                       answer            01/01/70 00:00      
                              as i said            01/01/70 00:00      
                                 lots of them            01/01/70 00:00      
                                 mcu with spi, right here in the thread            01/01/70 00:00      
                           CodeArchitect. ?            01/01/70 00:00      
                              no            01/01/70 00:00      
                                 ahhh            01/01/70 00:00      
      simulating SS?            01/01/70 00:00      
         Interrupts are slower than tight polling            01/01/70 00:00      
            wow            01/01/70 00:00      
               all about worst-case            01/01/70 00:00      
                  thanks...            01/01/70 00:00      
                     missed interrupts            01/01/70 00:00      
                        correct me..            01/01/70 00:00      
                           Fast interrupts            01/01/70 00:00      
                              thanks...            01/01/70 00:00      
                                 An Alternative...            01/01/70 00:00      
                                    Some Descriptive Information            01/01/70 00:00      
   AT89LP2052 has HW SPI            01/01/70 00:00      

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