| ??? 10/10/08 15:22 Modified: 10/10/08 15:45 Read: times |
#158958 - Some Descriptive Information Responding to: ???'s previous message |
Here is a link to a diagram that provides a detailed look at how interlocked handshaking works. In this diagram the handshake scheme shows transfers of 4-bit nibbles across four data wires in an interface. The scheme can be easily adapted to send on one data line at a time for serial data transfer. Also, as I described in the previous post it can be easily adapted, to support data transfer from slave to master during the same handshake sequence as master to slave is another data path is provided in the return direction. In this latter case the transfer would be very similar to the typical simultaneous out and in transfer that you may see for SPI.
http://www.carousel-design.com/NibbleMode.pdf Here is a link to a five years old posting here where I described a couple of projects where I have implemented this type of protocol. http://www.8052.com/forum/read.phtml?id=60707 Have Fun!! It can work well. Michael Karas |
| Topic | Author | Date |
| SPI slave | 01/01/70 00:00 | |
| high speed? | 01/01/70 00:00 | |
| sory for late replay. | 01/01/70 00:00 | |
| SPI clock | 01/01/70 00:00 | |
| not sure.. | 01/01/70 00:00 | |
| the worst possible approach | 01/01/70 00:00 | |
| SPI Slave Response | 01/01/70 00:00 | |
| further explanation? | 01/01/70 00:00 | |
| Fixed speed | 01/01/70 00:00 | |
| SPI Timing Diagrams | 01/01/70 00:00 | |
| UART Mode 0 - SPI like Serial Shif register | 01/01/70 00:00 | |
| uhm | 01/01/70 00:00 | |
| to joe | 01/01/70 00:00 | |
| your point? | 01/01/70 00:00 | |
| you can't fail with software master | 01/01/70 00:00 | |
| Unanswerable! | 01/01/70 00:00 | |
| really? | 01/01/70 00:00 | |
| Intended for/usable for not always identical | 01/01/70 00:00 | |
| consideration? | 01/01/70 00:00 | |
| Some Questions | 01/01/70 00:00 | |
| whichever you choose | 01/01/70 00:00 | |
| low cost? | 01/01/70 00:00 | |
| if you do not use an interrupt | 01/01/70 00:00 | |
| polling? | 01/01/70 00:00 | |
| bits/s not packet size | 01/01/70 00:00 | |
| speed? | 01/01/70 00:00 | |
| bits/s not packet size! | 01/01/70 00:00 | |
| 500ms? | 01/01/70 00:00 | |
| here | 01/01/70 00:00 | |
| Yes - I agree | 01/01/70 00:00 | |
| issues | 01/01/70 00:00 | |
| UART! | 01/01/70 00:00 | |
| Not complex - just requiring low baudrate | 01/01/70 00:00 | |
| kind of rcorrect | 01/01/70 00:00 | |
| Complexity contra recommendable | 01/01/70 00:00 | |
| answer | 01/01/70 00:00 | |
| as i said | 01/01/70 00:00 | |
| lots of them | 01/01/70 00:00 | |
mcu with spi, right here in the thread | 01/01/70 00:00 | |
| CodeArchitect. ? | 01/01/70 00:00 | |
| no | 01/01/70 00:00 | |
| ahhh | 01/01/70 00:00 | |
| simulating SS? | 01/01/70 00:00 | |
| Interrupts are slower than tight polling | 01/01/70 00:00 | |
| wow | 01/01/70 00:00 | |
| all about worst-case | 01/01/70 00:00 | |
| thanks... | 01/01/70 00:00 | |
| missed interrupts | 01/01/70 00:00 | |
| correct me.. | 01/01/70 00:00 | |
| Fast interrupts | 01/01/70 00:00 | |
| thanks... | 01/01/70 00:00 | |
| An Alternative... | 01/01/70 00:00 | |
| Some Descriptive Information | 01/01/70 00:00 | |
| AT89LP2052 has HW SPI | 01/01/70 00:00 |