The book you have is not a text, it's a data catalog for their devices.

Logic reduction, etc, e.g. Quine-McCluskey, Karnaugh mapping, and other techniques are discussed in logic circuits textbooks. That's all done automatically in the development software, and doing it manually seldom helps much, as the software generally reworks it for you despite your best efforts. The reason for this is that different device architectures require different fitting strategies in order to attain the best "fit" into their particular logic cell or lookup table configuration. The principles that made for really thrifty logic design when it was being done with TTL SSI/MSI devices are out the window when designing with fixed macrocell or logic cell structures that don't care how much of the lookup table or logic array you use once you use any part of it.

There's a book written by a fellow at Cypress that tries to serve as a VHDL text, but the main benefit of which is that it goes into considerable detail in describing the salient features of various manufacturers' devices. It shows the advantages and disadvantages of CPLD's, for example, as contrasted with FPGA's, and goes on to describe, at least in part, the advantage of ACTEL's structures and those of XILINX's. The author's name is Kevin Skahill, I believe. The one thing you must keep in mind when reading this book is that he worked for Cypress at the time, and they made CPLD's and not FPGA's.

RE