The synthesis tools offered by all three of these vendors, as well as third-party choices like Mentor Precision and Synplify, are up-to-date in terms of their VHDL features. You should be able to take advantage of the language's useful features (generic maps, generates, memory inference, etc) across all tools.

The biggest differences are with chip features. Some families offer dual-port RAMs, which the synthesis tools will happily infer (note: they can't infer dual-ports where ports have different word widths). Some families have cheap shift registers, which the tools will happily infer. For example, if the tool cannot infer a SRL16E, then it'll build one out of flip-flops. Of course, that eats resources and may not meet your ultimate timing goals, but often this is a desired result. Point is that you should understand what you're doing.

Things you usually can't infer are vendor- or family-specific features like clock-management blocks (DLLs, PLLs). You have to instantiate them. The good news is that you can use VHDL generates, and with a top-level generic you can select the appropriate component.

Of course, there are some features that a specific chip family may not have: if you need the hard PPC core found in certain Virtex-4 devices, then you're stuck.

It all depends on your design and your goals.

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